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--- resources:eval:user-guides:xud1a:user-guide [10 Dec 2021 20:23] – [Interposer Board] Sam Ringwood
+++ resources:eval:user-guides:xud1a:user-guide [19 May 2023 20:01] (current) – [Software/Digital Control] Sam Ringwood
@@ Line 1: / Line 1: @@
 ====== ADXUD1AEBZ (XUD1A) UP/DOWN CONVERTER BOARD ======
-====== UNDER CONSTRUCTION ======
 ====== General Description ======
@@ Line 7: / Line 6: @@
 The ADXUD1AEBZ consist of 4 channels capable of up and down conversion over a RF frequency band from 8 GHz to 12 GHz and IF frequency band from 4.2 GHz to 6.3 GHz. The RF input/outputs on the evaluation board are brought out to SMA coaxial connectors whereas the IF input/outputs are brought out to SMPM coaxial connectors specifically designated for transmit or receive. Digital control via GPIO and SPI lines are established through a PMOD connector with a compatible interposer board to allow [[adi>SDP-S|System Demonstration Platform (SDP-S)]] and FMC Mezzanine connector options. Control signals for the board are expected to be 1.8V logic with on-board level translators converting to the on-board logic level of 3.3V.
-{{ :resources:eval:user-guides:xud1a:xud1a_revc_top.jpg?400 |}}
+{{ :resources:eval:user-guides:xud1a:eval-adxud1aebz_top-web.gif?400 |}}
-<WRAP centeralign>**//Figure 1: ADXUD1AEBZ-EVAL1Z Board//**</WRAP>
+<WRAP centeralign>**//Figure 1: ADXUD1AEBZ Board: Front//**</WRAP>
+{{ :resources:eval:user-guides:xud1a:eval-adxud1aebz_bottom.jpg?400 |}}
+<WRAP centeralign>**//Figure 2: ADXUD1AEBZ Board: Back//**</WRAP>
 ----
@@ Line 22: / Line 24: @@
   * [[adi>media/en/technical-documentation/data-sheets/ADRF5020.pdf|ADRF5020 Datasheet]]
   * [[adi>media/en/technical-documentation/data-sheets/hmc652lp2-hmc655lp2.pdf|HMC652LP2E Datasheet]]
+  * ADXUD1AEBZ Rev. D Design:
+    * {{ :resources:eval:user-guides:xud1a:02-065073-01-d.pdf | Schematic}}
+    * {{ :resources:eval:user-guides:xud1a:xud1a_bom.zip |Bill of Materials}}
+  * Interposer Board Rev. A Design:
+    * {{ :resources:eval:user-guides:xud1a:02-067148-01-a.pdf | Schematic}}
+    * {{ :resources:eval:user-guides:xud1a:interposerbom.zip |Bill of Materials}}
+  * Interposer Board Rev. B Design:
+    * {{ :resources:eval:user-guides:xud1a:02-067148-01-b.pdf | Schematic}}
+    * {{ :resources:eval:user-guides:xud1a:interposerbom-b.zip |Bill of Materials}}
 ===== Hardware =====
@@ Line 27: / Line 39: @@
   * Interposer Board
   * SMA-SMA cabling to interface with the RF ports
-  * SMPM-SMA cabling to interface with the RF ports
+  * SMPM-SMA cabling to interface with the IF ports
   * Digital controller and any associated hardware ([[ADI>SDP-S]] or PMOD)
 <note warning>The SDP-S is the only SDP controller which will work with XUD1A. \\ \\
@@ Line 40: / Line 52: @@
 ===== Software/Digital Control =====
-=== SDP Control ===
-  * [[http://swdownloads.analog.com/ACE/SDP/SDPDrivers.exe|SDP Drivers]]
-  * {{ :resources:eval:user-guides:xud1a:sdp_xud1a.zip |Basic SDP Test Program}} (Windows 10 might try to block this, you'll have to explicitly allow it in your security settings)
-  * [[adi>sdp-s|SDP-S controller board]]
 === PMOD Control ===
   * Two 14-pin PMOD cables ([[https://www.digikey.com/en/products/detail/assmann-wsw-components/H3AKH-1406G/998997|Example]])
@@ Line 52: / Line 59: @@
     * [[https://www.arduino.cc/|Arduino]]
     * [[https://www.ftdichip.com/|FTDI]]
+=== SDP Control ===
+  * [[http://swdownloads.analog.com/ACE/SDP/SDPDrivers.exe|SDP Drivers]]
+  * {{ :resources:eval:user-guides:xud1a:sdp_xud1a.zip |Basic SDP-S Test Program Rev A}}
+  * {{ {{ :resources:eval:user-guides:xud1a:sdps_xud1a_r1.zip | Basic SDP-S Test Program Rev B}}
+<note>Windows 10 might try to block the example Test Program, you'll have to explicitly allow it in your security settings</note>
+  * [[adi>sdp-s|SDP-S controller board]]
 === Software ===
@@ Line 74: / Line 88: @@
 The ADXUD1AEBZ has 4 RF input/output SMA connectors and 4 TX IF inputs and 4 RX IF outputs via SMPM connectors. Each RF channel is bandpass filtered and tied to two [[adi>ADRF5020|ADRF5020]] switches with independent [[adi>hmc903lp3e|HMC903]] amplifiers for TX and RX. Up/down conversion is accomplished using the [[adi>hmc773alc3b|HMC773A]] with the option to drive the LO either externally via the J4 SMA connector or internally with the [[adi>adf4371|ADF4371]]. The RX IF channel is amplified by the [[adi>ADL8111|ADL8111]] and [[adi>hmc8411|HMC8411]] whereas the TX IF channel is internally bypassed by the [[adi>ADL8111|ADL8111]].
-{{ :resources:eval:user-guides:xud1a:xud1a_revc_blockdiagram.png |}}
+{{ :resources:eval:user-guides:xud1a:xud1a_revd_blockdiagram.png |}}
-<WRAP centeralign>**//Figure 2: ADXUD1AEBZ Block Diagram//**</WRAP>
+<WRAP centeralign>**//Figure 3: ADXUD1AEBZ Block Diagram//**</WRAP>
 ===== LO Signal Chain =====
@@ Line 82: / Line 96: @@
 By default, the board populates C165 for an external LO source with C61 not installed. The user can remove C165 and re-install on the C61 pad to enabled use of the ADF4371. When using the onboard ADF4371, the default reference is the onboard VCXO with C372 installed and C373 not installed. The user can remove C372 and re-install on the C373 pad to enabled use of the external reference port J3.
+<note>An external LO source is recommended for performance based measurements. The on-board ADF4371 is provided for convenience to allow stand-alone operation of the hardware for a wide range of operational frequencies. A bandpass filter should be inserted in the ADF4371 PLL output path depending on the final frequency plan to reject the harmonic content generated by the ADF4371 internal multipliers.</note>
 ===== Digital Control =====
 ==== PMOD Pinout ====
-The digital input signals are intended to be 1.8V logic while the [[adi>ADRF5020|ADRF5020]], [[adi>ADL8111|ADL8111]], and [adi>adf4371|ADF4371]] digital control inputs require logic levels of 3.3V. Level translators and digital logic circuitry have been included between the PMOD connector and aforementioned components.
+The digital input signals are intended to be 1.8V logic while the [[adi>ADRF5020|ADRF5020]], [[adi>ADL8111|ADL8111]], and [[adi>ADF4371|ADF4371]] digital control inputs require logic levels of 3.3V. Level translators and digital logic circuitry have been included between the PMOD connector and aforementioned components.
 {{ :resources:eval:user-guides:xud1a:xud1a_pmod.png?400 |}}
-<WRAP centeralign>**//Figure 3: ADXUD1AEBZ PMOD Pinout//**</WRAP>
+<WRAP centeralign>**//Figure 4: ADXUD1AEBZ PMOD Pinout//**</WRAP>
 ==== Interposer Board ====
@@ Line 93: / Line 108: @@
 {{ :resources:eval:user-guides:xud1a:xud1a_sdps.png? |}}
-<WRAP centeralign>**//Figure 4: ADXUD1AEBZ Interposer Pinout with SDP-S Connector//**</WRAP>
+<WRAP centeralign>**//Figure 5: ADXUD1AEBZ Interposer Pinout with SDP-S Connector//**</WRAP>
-{{ :resources:eval:user-guides:xud1a:xud1a_fmc.png? |}}
+==== Control Logic ====
-<WRAP centeralign>**//Figure 5: ADXUD1AEBZ Interposer Pinout with FMC Connector//**</WRAP>
+The PMOD inputs are fed to a buffer and logic network for simplified board control and quick switching time.
+{{ :resources:eval:user-guides:xud1a:xud1a_controlblockdiagram.png?600 |}}
+<WRAP centeralign>**//Figure 6: ADXUD1AEBZ Control Block Diagram//**</WRAP>
+^ Channel ^  Mode  ^ TXRX0 ^ TXRX1 ^ TXRX2 ^ TXRX3 ^ Rx Gain Mode ^
+|     A    |    TX    |    1    |    -    |    -    |    -    |    0    |
+|     :::    |    RX Low Gain    |    0    |    -    |    -    |    -    |    0    |
+|     :::    |    RX High Gain    |    0    |    -    |    -    |    -    |    1    |
+|     B    |    TX    |    -    |    1    |    -    |    -    |    0    |
+|     :::    |    RX Low Gain    |    -    |    0    |    -    |    -    |    0    |
+|     :::    |    RX High Gain    |    -    |    0    |    -    |    -    |    1    |
+|     C    |    TX    |    -    |    -    |    1    |    -    |    0    |
+|     :::    |    RX Low Gain    |    -    |    -    |    0    |    -    |    0    |
+|     :::    |    RX High Gain    |    -    |    -    |    0    |    -    |    1    |
+|     D    |    TX    |    -    |    -    |    -    |    1    |    0    |
+|     :::    |    RX Low Gain    |    -    |    -    |    -    |    0    |    0    |
+|     :::    |    RX High Gain    |    -    |    -    |    -    |    0    |    1    |
+<WRAP centeralign>**//Table 1: ADXUD1AEBZ RF Control Logic//**</WRAP>
+^  ADF4371 Output  ^  PLL_OUTPUT_SEL  ^
+|     8 - 16 GHz    |    1   |
+|     16 - 32 GHz    |    0   |
+<WRAP centeralign>**//Table 2: ADXUD1AEBZ ADF4371 Control Logic//**</WRAP>
 ====== Evaluation ======
 ===== Software Control =====
 There are two methods to control the XUD1A board using the interposer board. Either over the FMC connector using the ZCU102 FPGA or over the SDP connector using a SDP-S controller. Limited functionality is available using the SDP-s controller, but a user has the basic ability to program the state of XUD1A (TX, RX Low Gain, RX High Gain) using the SPD-S controller.
-<note>If using the SDP-S controller to control XUD1A, then install the EEPROM Programmer software and connect the SDP-S controller board. Load the XUD1A.dat file into the File Path of the EEPROM Programmer software. Write the EEPROM. Disconnect from the EEPROM Programmer to use with XUD1A.</note>
 ===== Standalone Python Application =====
 Download the application from the [[#Software|Software]] section.  Extract the file contents to your desired PC drive.  It is recommended to save the folder to your root drive for simplicity. Using your preferred command terminal, change the directory to the desired state folder (e.g. >> cd C:/XUD1A_ctrl/TX). Execute the application through the terminal window.
+===== Support =====
+For additional questions or support, please visit the Engineering Zone forum at [[ez>ADEF]].
+[[resources/eval/user-guides/xud1a|ADXUD1AEBZ Homepage]]
+[[:resources:eval:user-guides:x-band-platform|X Band Development Platform]]

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