This version is outdated by a newer approved version.
This version (11 Nov 2021 17:20) is a draft.
Approvals: 0/1The Previously approved version (13 Oct 2021 03:44) is available.
This version (11 Nov 2021 17:20) is a draft.Approvals: 0/1The Previously approved version (13 Oct 2021 03:44) is available.
This is an old revision of the document!
Table of Contents
ADXUD1AEBZ (XUD1A) UP/DOWN CONVERTER BOARD
UNDER CONSTRUCTION
General Description
The ADXUD1AEBZ evaluation board is a quad channel Up and Down converter designed for X Band general purpose use. The complete Analog Devices solution chain consist of amplifiers, LNAs, switches, mixers, integrated PLL/VCO, and power management circuitry all powered by a single +12V power supply. Frequency conversion can be accomplished using either the integrated PLL/VCO or an external LO. This evaluation board is intended to be used with an external Low Noise Amplifier and Power Amplifier to set the desired noise figure and output power of the user's signal chain.
The ADXUD1AEBZ consist of 4 channels capable of up and down conversion over a RF frequency band from 8 GHz to 12 GHz and IF frequency band from 4.2 GHz to 6.3 GHz. The RF input/outputs on the evaluation board are brought out to SMA coaxial connectors whereas the IF input/outputs are brought out to SMPM coaxial connectors specifically designated for transmit or receive. Digital control via GPIO and SPI lines are established through a PMOD connector with a compatible interposer board to allow System Demonstration Platform (SDP-S) and FMC Mezzanine connector options. Control signals for the board are expected to be 1.8V logic with on-board level translators converting to the on-board logic level of 3.3V.
Figure 1: ADXUD1AEBZ-EVAL1Z Board
REQUIREMENTS
Documents
Hardware
- ADXUD1AEBZ
- Interposer Board
- SMA-SMA cabling to interface with the RF ports
- SMPM-SMA cabling to interface with the RF ports
- Digital controller and any associated hardware (SDP-S or PMOD)
The SDP-S is the only SDP controller which will work with XUD1A.
All other SDP controllers (SDP-B, SDP-H1, SDP-K1) are NOT compatible.
All other SDP controllers (SDP-B, SDP-H1, SDP-K1) are NOT compatible.
Suggested Test Equipment
- 20GHz RF Signal Generator (2x)
- 20GHz Spectrum Analyzer
- 20GHz Vector Network Analyzer (optional)
- Oscilloscope (optional)
- RF Power Meter (optional)
Software/Digital Control
SDP Control
- Basic SDP Test Program (Windows 10 might try to block this, you'll have to explicitly allow it in your security settings)
PMOD Control
- Two 14-pin PMOD cables (Example)
- Example PMOD digital controllers:
- FPGA demonstration board
Software
- PyADI-IIO interface for LibIIO
Board Design
The ADXUD1AEBZ evaluation board has 4 SMA RFIO connectors for the RF Input/Output and 8 SMPM RFIO connectors for the IF Input/Output. The 8 SMPM connectors have 4 RX IF channels and 4 TX IF channels. There is 1 SMA connector available to supply an external LO signal. The board is configured for an external LO by default. A capacitor can be rotated to disable the external LO port and access the internal PLL/VCO (ADF4371). The PLL/VCO can be programmed via SPI to allow an on-board LO signal.
One 12V DC barrel jack is provided to apply the required 12V power supply with on-board power management circuitry to converter to the necessary power rails.
One 14 PIN PMOD connector is provided to apply GPIO/SPI digital control lines.
Power Supply
The ADXUD1AEBZ board must be powered from the included power supply with a voltage level of 12V. There is an on-board power management tree which generates the required voltage rails for all of the associated parts.
RF/IF Signal Chain
The ADXUD1AEBZ has 4 RF input/output SMA connectors and 4 TX IF inputs and 4 RX IF outputs via SMPM connectors. Each RF channel is bandpass filtered and tied to two ADRF5020 switches with independent HMC903 amplifiers for TX and RX. Up/down conversion is accomplished using the HMC773A with the option to drive the LO either externally via the J4 SMA connector or internally with the ADF4371. The RX IF channel is amplified by the ADL8111 and HMC8411 whereas the TX IF channel is bypassed by the ADL8111.
Figure 2: ADXUD1AEBZ Block Diagram
LO Signal Chain
The LO signal is amplified by HMC963 and HMC383 amplifiers and divided across all channels to provide a common LO signal. The user can decide between an internal PLL or external LO. The internal PLL is the ADF4371 with an option for an external reference via J3 connector or an on-board VCXO reference. An external LO source can be injected via the J4 SMA connector. When using an external LO, the recommended input power to J4 is +5 dBm.
By default, the board populates C165 for an external LO source with C61 not installed. The user can remove C165 and re-install on the C61 pad to enabled use of the ADF4371. When using the onboard ADF4371, the default reference is the onboard VCXO with C372 installed and C373 not installed. The user can remove C372 and re-install on the C373 pad to enabled use of the external reference port J3.
Digital Signals
The digital input signals are intended to be 1.8V logic while the ADRF5020 and ADL8111 digital control inputs require logic levels of 3.3V. Level translators and digital logic circuitry have been included between the PMOD connector and aforementioned components.
Figure 3: ADXUD1AEBZ PMOD Pinout
Evaluation
resources/eval/user-guides/xud1a/user-guide.1636647600.txt.gz · Last modified: 11 Nov 2021 17:20 by Sam Ringwood