Following the success of Voyager3, Voyager4 now offers AI processing and generation of insights right on the edge, transmitting its insides via Bluetooth Low Energy and ultra-low-power microcontrollers.
The system's hardware is constitued of:
In normal mode the MAX32666 logic enables the 3.3V1 & 3.3V3 power rails, and the MAX38642, which power the MAX78000, ADXL359, and SPH0645LM4H-B. The MAX78000 bootloader can be accessed over I2C using the FTDI Chip. The bootloader can be used to disable the MAX78000 SWD interface to block debug port access. This provides IP protection/security for the user.
Voyager4 Offers an innovative state-of-the-art autoencoder machine learning model to classify faults according to the gathered data.
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TIP: upload the .svg file for the diagram to have high quality
Only the channels presented in the clocking selection are relevant. For the rest, you can either disable them or just put a divided frequency of the source clock.
Analog Devices will provide limited online support for anyone using the reference design with Analog Devices components via the EngineerZone FPGA reference designs forum.
It should be noted, that the older the tools' versions and release branches are, the lower the chances to receive support from ADI engineers.