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Quad-MxFE Prototyping Platform User Guide

Product Details

The Quad-MxFE System Development Platform contains four MxFE™ software defined, direct RF sampling transceivers, as well as associated RF front-ends, clocking, and power circuitry. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a 16 transmit/16 receive channel direct sampling phased array at L/S/C band (0.1 GHz to ~5GHz). The Rx & Tx RF front-end has drop-in configurations that allow for customized frequency ranges, depending on the user’s application.

The Quad-MxFE System Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating multi-chip synchronization as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a VCU118 Evaluation Board from Xilinx®, which features the Virtex® UltraScale+™ XCVU9P FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing.

In addition to the Quad-MxFE Digitizing Card, the kit also contains a 16Tx/16Rx Calibration Board that is used to develop system-level calibration algorithms, or otherwise more easily demonstrate power-up phase determinism in situations pertinent to their own use case. The Calibration Board also allows the user to demonstrate combined-channel dynamic range, spurious, and phase noise improvements and can also be controlled via a free MATLAB add-on when connected to the PMOD interface of the VCU118.

The system can be used to enable quick time-to-market development programs for applications like:

  • ADEF (Phased-Array, RADAR, EW, SATCOM)
  • Communications Infrastructure (Multiband 5G and mmWave 5G)
  • Electronic Test and Measurement

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User Resources

Features

  • Multi-channel, wideband system development platform for the AD9081 MxFE™
  • Mates with Xilinx VCU118 Evaluation Board (Not Included)
  • 16x RF Receive (Rx) Channels (32x Digital Rx Channels)
    • Total 16x 1.5GSPS to 4GSPS ADC
    • 48x Digital Down Converters (DDCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
    • 16x Programmable Finite Impulse Response Filters (pFIRs)
  • 16x RF Transmit (Tx) Channels (32x Digital Tx Channels)
    • Total 16x 3GSPS to 12GSPS DAC
    • 48x Digital Up Converters (DUCs) , Each Including Complex Numerically-Controlled Oscillators (NCOs)
  • Flexible Rx & Tx RF Front-Ends
    • Rx: Filtering, Amplification, Digital Step Attenuation for Gain Control
    • Tx: Filtering, Amplification
  • Multiple System Control and Analysis Tools
    • IIO Oscilloscope GUI
    • MATLAB Add-Ons & Example Scripts
    • HDL and Embedded Software Solutions for JESD204b/JESD204c Bring-Up
  • Provided Application-Specific Examples
    • Multi-Chip Synchronization for Power-Up Phase Determinism
    • System-Level Amplitude/Phase Alignment Using NCOs
    • Low-Latency ADC-to-DAC Loopback Bypassing JESD Interface
    • pFIR Control for Broadband Channel-to-Channel Amplitude/Phase Alignment
    • Fast-Frequency Hopping
  • On-Board Power Regulation from Single 12V Power Adapter (Included)
  • Flexible Clock Distribution
    • On-Board Clock Distribution from Single External 500MHz Reference
    • Support for External Converter Clock
  • On-board power regulation from 12V power adaptor (included)

General Description

This user guide serves as the main source of information for system engineers and software developers using the Quad-MxFE System Evaluation Board, which contains four AD9081 software defined, direct RF sampling transceivers, as well as associated RF front-end, clocking, and power circuitry. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a 16 transmit/16 receive channel direct sampling phased array at L/S/C band (0.1 GHz to ~5GHz). The Rx & Tx RF front-end has drop-in configurations that allow for customized frequency ranges, depending on the user’s application.

The Quad-MxFE System Evaluation Board highlights a complete system solution. It is intended as a testbed for demonstrating multi-chip synchronization as well as implementation of system level calibrations, beam forming algorithms, and other signal processing algorithms. The board is designed to mate with a VCU118 Evaluation Board from Xilinx®, which features the Virtex® UltraScale+™ XCVU9P FPGA, with provided reference software and HDL code.

High-Level Block Diagram

System Integration

Below is the full integrated system including the VCU118, ADQUADMXFE1EBZ, and ADQUADMXFE-CAL in full operation.

Key Component Locations

LED Status Indicators

Publications

MxFE

ADF4371

HMC7043

LTM4633

LTM8063

LTM8053

FPGA Evaluation Board Hardware

Questions

For additional questions or support, please visit the Engineering Zone forum at adef.


resources/eval/user-guides/quadmxfe.1616790580.txt.gz · Last modified: 26 Mar 2021 21:29 by Chas Frick