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| resources:eval:user-guides:quadmxfe [20 Jan 2021 22:32] – [LED Status Indicators] Michael Stetzler | resources:eval:user-guides:quadmxfe [14 Nov 2023 10:13] (current) – Change branch for link iulia Moldovan |
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| ===== Product Details ===== | ===== Product Details ===== |
| The Quad-MxFE System Development Platform contains four [[adi>/en/products/digital-to-analog-converters/high-speed-da-converters/mixed-signal-frontends.html|MxFE™]] software defined, direct RF sampling transceivers, as well as associated RF front-ends, clocking, and power circuitry. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a **16 transmit/16 receive channel** direct sampling phased array at L/S/C band (0.1 GHz to ~5GHz). The Rx & Tx RF front-end has drop-in configurations that allow for customized frequency ranges, depending on the user’s application. | The [[adi>/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/Quad-MxFE.html|Quad-MxFE System Development Platform]] contains four [[adi>/en/products/digital-to-analog-converters/high-speed-da-converters/mixed-signal-frontends.html|MxFE™]] software defined, direct RF sampling transceivers, as well as associated RF front-ends, clocking, and power circuitry. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a **16 transmit/16 receive channel** direct sampling phased array at L/S/C band (0.1 GHz to ~5GHz). The Rx & Tx RF front-end has drop-in configurations that allow for customized frequency ranges, depending on the user’s application. |
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| The Quad-MxFE System Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating multi-chip synchronization as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a [[xilinx>VCU118]] Evaluation Board from Xilinx®, which features the Virtex® UltraScale+™ XCVU9P FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing. | The Quad-MxFE System Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating multi-chip synchronization as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a [[xilinx>VCU118]] Evaluation Board from Xilinx®, which features the Virtex® UltraScale+™ XCVU9P FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing. |
| * Electronic Test and Measurement | * Electronic Test and Measurement |
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| | {{:resources:eval:user-guides:adquadmxfe1ebztop-web.gif}} |
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| {{ :resources:eval:user-guides:board_top_edited.jpg |}} | |
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| {{ analogTV>6184061669001 }} | {{ analogTV>6184061669001 }} |
| - [[resources:eval:user-guides:quadmxfe#features|System Features]] | - [[resources:eval:user-guides:quadmxfe#features|System Features]] |
| - [[resources:eval:user-guides:quadmxfe#general_description|General Description]] | - [[resources:eval:user-guides:quadmxfe#general_description|General Description]] |
| * [[resources:eval:user-guides:quadmxfe:quickbringup|Getting Started]] | * [[resources:eval:user-guides:quadmxfe:quickbringup|Getting Started]] - **Install Fan/Heat Sinks Prior To First Use!** |
| - [[resources:eval:user-guides:quadmxfe:quickbringup#equipment_needed|Equipment Needed]] | - [[resources:eval:user-guides:quadmxfe:quickbringup#equipment_needed|Equipment Needed]] |
| - [[resources:eval:user-guides:quadmxfe:quickbringup#software_needed|Required Software]] | - [[resources:eval:user-guides:quadmxfe:quickbringup#software_needed|Required Software]] |
| - [[resources:eval:user-guides:quadmxfe:boardhardwaredetails#schematic|Schematic]] | - [[resources:eval:user-guides:quadmxfe:boardhardwaredetails#schematic|Schematic]] |
| * [[resources:eval:user-guides:ad_quadmxfe1_ebz:ad_quadmxfe1_ebz_hdl|HDL]] | * [[resources:eval:user-guides:ad_quadmxfe1_ebz:ad_quadmxfe1_ebz_hdl|HDL]] |
| - [[https://github.com/analogdevicesinc/hdl/tree/dev_mxfe_c/projects/ad_quadmxfe1_ebz|Quad-MxFE HDL Reference Design]] | - [[repo>hdl/tree/dev_quad_mxfe_revab/projects/ad_quadmxfe1_ebz|Rev A/B. Quad-MxFE HDL Reference Design]] |
| | - [[repo>hdl/tree/main/projects/ad_quadmxfe1_ebz|Rev C. Quad-MxFE HDL Reference Design]] |
| * [[resources:eval:user-guides:quadmxfe:multichipsynchronization|Multi-Chip Synchronization Guide]] | * [[resources:eval:user-guides:quadmxfe:multichipsynchronization|Multi-Chip Synchronization Guide]] |
| * [[resources:eval:user-guides:quadmxfe#related_documents|Related Documents]] | * [[resources:eval:user-guides:quadmxfe#related_documents|Related Documents]] |
| * On-Board Clock Distribution from Single External 500MHz Reference | * On-Board Clock Distribution from Single External 500MHz Reference |
| * Support for External Converter Clock | * Support for External Converter Clock |
| * On-board power regulation from 12V power adaptor (included) | |
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| ==== System Integration ==== | ==== System Integration ==== |
| Below is the full integrated system including the [[xilinx> Xilinx VCU118]], ADQUADMXFE1EBZ, and [[resources:eval:user-guides:quadmxfe:calboard|ADQUADMXFE-CAL]] in full operation. | Below is the full integrated system including the [[xilinx>VCU118]], ADQUADMXFE1EBZ, and [[resources:eval:user-guides:quadmxfe:calboard|ADQUADMXFE-CAL]] in full operation. |
| {{ :resources:eval:user-guides:quadfull_edit.jpg |}} | {{ :resources:eval:user-guides:quadfull_edit.jpg |}} |
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| ==== Key Component Locations ==== | ==== Key Component Locations ==== |
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| {{ :resources:eval:user-guides:board_top_edited_labeled.jpg |}} | {{:resources:eval:user-guides:quad_mxfe_labels_top.jpg|}} |
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| {{ :resources:eval:user-guides:board_bottom_edited_2.jpg |}} | {{:resources:eval:user-guides:quad_mxfe_labels_bottom.jpg|}} |
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| * [[/resources/eval/user-guides/quadmxfe/boardhardwaredetails#power_leds|Power (Green) LED Information]] | * [[/resources/eval/user-guides/quadmxfe/boardhardwaredetails#power_leds| Quad MxFE Power (Green) LED Information]] |
| * [[/resources/eval/user-guides/quadmxfe/boardhardwaredetails#clock_leds|Clock (Blue) LED Information]] | * [[/resources/eval/user-guides/quadmxfe/boardhardwaredetails#clock_leds| Quad MxFE Clock (Blue) LED Information]] |
| * [[/resources/eval/user-guides/quadmxfe/calboard#led_identification | Calibration Broad LED Information]] | * [[/resources/eval/user-guides/quadmxfe/calboard#led_identification | Calibration Broad LED Information]] |
| * [[xilinx>support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf | VCU118 LED Information (pg. 85)]] | * [[xilinx>support/documentation/boards_and_kits/vcu118/ug1224-vcu118-eval-bd.pdf | VCU118 LED Information (pg. 85)]] |
| * [[adi>/en/design-notes/multichannel-rf-to-bits-development-platform.html|Multichannel RF to Bits Development Platform]] | * [[adi>/en/design-notes/multichannel-rf-to-bits-development-platform.html|Multichannel RF to Bits Development Platform]] |
| * [[adi>en/technical-articles/power-up-phase-determinism-using-multichip-synchronization.html|Power-Up Phase Determinism Using Multichip Synchronization Features in Integrated Wideband DACs and ADCs]] | * [[adi>en/technical-articles/power-up-phase-determinism-using-multichip-synchronization.html|Power-Up Phase Determinism Using Multichip Synchronization Features in Integrated Wideband DACs and ADCs]] |
| | * [[adi>en/technical-articles/integrated-hardened-dsp-on-dac-adc-ics-improves-wideband-multichannel-systems.html|Integrated Hardened DSP on DAC/ADC ICs Improves Wideband Multichannel Systems]] |
| | * [[adi>en/education/education-library/webcasts/multi-channel-system-improvements-using-hardened-dsp-digitizer-ics.html|Multi-Channel System Improvements Using Hardened DSP in Digitizer ICs]] |
| | * [[adi>en/technical-articles/empirical-based-multichannel-phase-noise-model.html|Empirically Based Multichannel Phase Noise Model Validated in a 16-Channel Demonstrator]] |
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| ==== Related Part Pages ==== | ==== Related Part Pages ==== |
| * [[adi>/en/products/ad9081.html|AD9081]] | * [[adi>/en/products/ad9081.html|AD9081]] |
| * [[adi>/en/products/ad9082.html|AD9082]] | * [[adi>/en/products/ad9082.html|AD9082]] |
| * [[resources:eval:ad9082|EVALUATING THE AD9082 / AD9081 Mixed-Signal Front-End (MxFE™) RF Transceiver]] | * [[:resources:eval:user-guides:ad9081_fmca_ebz:quickstart:zynqmp|AD9081/AD9082 Zynq UltraScale+ MPSoC ZCU102 Quick Start Guide]] |
| * [[adi>/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf|UG-1578 User Guide]] | * [[adi>/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf|UG-1578 User Guide]] |
| === ADF4371 === | === ADF4371 === |
| * [[xilinx>/products/boards-and-kits/vcu118.html|Xilinx Virtex UltraScale+ FPGA VCU118]] | * [[xilinx>/products/boards-and-kits/vcu118.html|Xilinx Virtex UltraScale+ FPGA VCU118]] |
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| | ===== Questions ===== |
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| | For additional questions or support, please visit the Engineering Zone forum at [[ez>adef-system-platforms/]]. |
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