The main IIO interface is provided in the install of IIO Oscilloscope which uses LibIIO to communicate through IIO to the chips on the Quad MxFE board. The install process for IIO Oscilloscope and a walkthrough of opening the program can be found here: Quick Start IIO Oscilloscope.
MATLAB is used to exercise the board through LibIIO objects and provide higher level application functionality. In order to work with the platform, a number of toolboxes and support packages are required:
PuTTY helps to provide a view into the Linux and give additional controls and debug abilities. Putty can be downloaded from here Putty Download Page. Ensure that the proper version for the computer is downloaded (64 bit for a 64 bit PC). Once downloaded the COM port to the FPGA can be opened. This COM port can be identified through the device manager as the standard COM port:
In order to program the FPGA, the Vivado tool suite is required: Vivado Toolchain. Grab the Self Extracting Web Installer and run the installer. The full version should be installed. If licensing is an issue, then use the Lab Tools edition and make sure to install the Xilinx SDK toolset as well which available through the Vitis platform here: Vitis Platform
The software programming process is similar to the process detailed here: Programming FPGA. However the steps in Windows are a bit different. Mainly, the settings file does not need to be sourced as in Linux. There is also potentially a change of directory to the location of the
.tcl files which specify the image to be programmed. Once these commands below have been issued, the rest of the output on Windows will be very similar to the Linux output.
Xilinx Software Commandline Tool (XSCT) v2019.1 Build date : May 24 2019-15:06:52 Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. xsct% cd Desktop/Quad_Mxfe_Files xsct% source run.vcu118_quad_ad9081_204b_txmode_9_rxmode_10.tcl
The required FPGA files and
.tcl scripts can be downloaded from here:
Once downloaded, unzip these files to a convenient directory (this directory will be used in XSCT).
This section assumes the following:
192.168.2.1. This assumes that the USB to Ethernet dongle has been configured with an IP address of
xrepresents a number 0 to 255 (excluding 1). This can be seen in the image. These settings are accessed (in Windows 10) by typing Network into the start menu then choose the “change adapter options” select and right click on the USB to Ethernet dongle. Select properties from the right click menu. Once the IP has been set, it will be remembered on the computer. Click ok on both windows to close and save the Dongle IP settings.
The power up sequence is not difficult:
Once these are powered up, program the FPGA:
If the files were unzipped somewhere else, then change directory to that folder.
The statement above will launch the programming of the first build, but the others can be run by changing the name of the particular .tcl file to be loaded
UN: root PW: analog
Device Selection, select the IIO device which should be debugged/controlled.
IIO Device Attribute section, all device and channel attributes can be read or written,
including all attributes which are not handled by the
AD9081-X device plugin itself.
Register section select source
Detailed Register Map and
AutoRead, this will enable a complete AD9081 register view with description bitfields and dropdown options if available.
axi-ad9081-rx-3 are again special, since beside the SPI option they also can access the AXI_CORE register space of the transport layer core.
If no blue lights are visible on the board, then the PLLs are not locked. The most likely cause of this is the lack of a 500MHz source into J41. Check the input power and state of the source. It should be 500MHz @ ~0dBm. Once the 500MHz signal is verified, the FPGA programming must be rerun.