This version (18 Sep 2020 22:56) was approved by wmjones2.The Previously approved version (15 Sep 2020 09:26) is available.Diff

Software Quick Start Guide (Supported JESD Modes)

Software Needed


The main IIO interface is provided in the install of IIO Oscilloscope which uses LibIIO to communicate through IIO to the chips on the Quad MxFE board. The install process for IIO Oscilloscope and a walkthrough of opening the program can be found here: Quick Start IIO Oscilloscope.

MATLAB 2019b or 2020a (Optional)

MATLAB is used to exercise the board through LibIIO objects and provide higher level application functionality. In order to work with the platform, a number of toolboxes and support packages are required:

  1. Communications Toolbox. Installed through MATLAB Add Ons page.
  2. Communications Toolbox Support Package for Xilinx Zynq-Based Radio. Installed through MATLAB Add Ons page.
  3. AnalogDevicesHighSpeedConverterToolbox. Can be installed through Add Ons page or latest version here: High Speed Converter Toolbox Download Page


PuTTY helps to provide a view into the Linux and give additional controls and debug abilities. Putty can be downloaded from here Putty Download Page. Ensure that the proper version for the computer is downloaded (64 bit for a 64 bit PC). Once downloaded the COM port to the FPGA can be opened. This COM port can be identified through the device manager as the standard COM port:

In PuTTY, this should be opened with a baudrate of 115200.

Xilinx Software Command Line Tool (XSCT)

In order to program the FPGA, the Vivado tool suite is required: Vivado Toolchain. Grab the Self Extracting Web Installer and run the installer. The full version should be installed. If licensing is an issue, then use the Lab Tools edition and make sure to install the Xilinx SDK toolset as well which available through the Vitis platform here: Vitis Platform

The software programming process is similar to the process detailed here: Programming FPGA. However the steps in Windows are a bit different. Mainly, the settings file does not need to be sourced as in Linux. There is also potentially a change of directory to the location of the .tcl files which specify the image to be programmed. Once these commands below have been issued, the rest of the output on Windows will be very similar to the Linux output.

 Xilinx Software Commandline Tool (XSCT) v2019.1
   Build date : May 24 2019-15:06:52
     Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

xsct% cd Desktop/Quad_Mxfe_Files
xsct% source run.vcu118_quad_ad9081_204b_txmode_9_rxmode_10.tcl 


The required FPGA files and .tcl scripts can be downloaded from here:

Once downloaded, unzip these files to a convenient directory (this directory will be used in XSCT).

Quick Start Bringup with Hardware

This section assumes the following:

  1. Standoffs have been attached to Quad MxFE board
  2. VCU118 and Quad MxFE have been attached via a FMC+ extender on the FMC+
  3. Ethernet cable has been connected to VCU118 and connected to USB to Ethernet
  4. USB to Ethernet dongle has IP address of For locally connected FPGAs (i.e. Ethernet cable from VCU118 to USB to Ethernet dongle), the Hostname is This assumes that the USB to Ethernet dongle has been configured with an IP address of 192.168.2.x where x represents a number 0 to 255 (excluding 1). This can be seen in the image. These settings are accessed (in Windows 10) by typing Network into the start menu then choose the “change adapter options” select and right click on the USB to Ethernet dongle. Select properties from the right click menu. Once the IP has been set, it will be remembered on the computer. Click ok on both windows to close and save the Dongle IP settings.

 Configuration of USB to Ethernet Dongle IP

  1. 2x micro USB cables have been connected to PC and VCU118 for JTAG and Serial
  2. All required software programs have been installed. See here for full list: Software Needed
  3. All FPGA images/script files have been downloaded and unzipped to a folder on the Desktop called QuadMxFE
  4. 500MHz ~0dBm source has been attached to Quad MxFE central clock input SMA
  5. 12V power bricks (>8A for Quad MxFE and >5A for VCU118) have been connected to boards

General Board Power Up/Programming Sequence

The power up sequence is not difficult:

  1. Power up the Quad MxFE Board
  2. Power up the 500MHz oscillator
  3. Power on the VCU118 board

Once these are powered up, program the FPGA:

  1. Open Putty at the correct COM port and baudrate of 115200. See this section to determine the correct COM port Putty Configuration
  2. Open Xilinx Command Line Tool (XSCT). Type “xi” into start menu and you should find the command line tool if installed correctly. Once the prompt is open, type:
    cd C:\Users\<username>\Desktop\QuadMxFE

    If the files were unzipped somewhere else, then change directory to that folder.

  3. Run the loading script for the particular build by typing the following (example) in XSCT:
    source run.vcu118_quad_ad9081_204b_txmode_11_rxmode_4.tcl

    The statement above will launch the programming of the first build, but the others can be run by changing the name of the particular .tcl file to be loaded

  4. Wait for the programming to finish in XSCT. This should show that the tcfchan#1 was closed as the final step.
  5. Wait for the build to boot completely by checking the Putty terminal window. The putty window shows the progress of the Linux image booting. Wait for the login prompt as shown at the bottom. This example outputs is from the Txmode 11 Rxmode 4 image output. At this point, the image is ready to use in MATLAB or additional debug steps can be performed. To log into the image, the username and password are
    UN: root 
    PW: analog
  6. At this point the FPGA has booted and all of the blue PLL lights should be illuminated. The FPGA is ready to be controlled from MATLAB or from IIO Oscilloscope.
  7. To work in IIO Oscilloscope, open IIO Oscilloscope and use the GUI
  8. To control through MATLAB, open the script that matches the name of the .tcl file that was run in XSCT. Once this script is open, run the script from the top of the MATLAB editor or hit F5 to run the script.

MATLAB Script Overview

The following plots show the output of the calibration routine without a calibration board.


Under Device Selection, select the IIO device which should be debugged/controlled.

In the IIO Device Attribute section, all device and channel attributes can be read or written,

including all attributes which are not handled by the AD9081-X device plugin itself.

In the Register section select source SPI, check Detailed Register Map and AutoRead, this will enable a complete AD9081 register view with description bitfields and dropdown options if available.

IIO devices axi-ad9081-tx-3 and axi-ad9081-rx-3 are again special, since beside the SPI option they also can access the AXI_CORE register space of the transport layer core.

No blue lights are visible on board

If no blue lights are visible on the board, then the PLLs are not locked. The most likely cause of this is the lack of a 500MHz source into J41. Check the input power and state of the source. It should be 500MHz @ ~0dBm. Once the 500MHz signal is verified, the FPGA programming must be rerun.




resources/eval/user-guides/quadmxfe/quickbringup.txt · Last modified: 18 Sep 2020 22:56 by wmjones2