The 16x transmit front-ends are all on the bottom of the board and contain identical components. The Tx front-end is comprised of a balun for differential to single-ended transitioning, a filter, and an HMC8411 RF amplifier to serve as a modest gain stage for any downstream peripherals. The transmit signals are launched off the board via an MMCX connector.
Within the digital domain, the transmit path receives a data stream from the JESD204b/c interface and then has the option to traverse through 8x fine or 4x coarse digital up-converters (DUCs) prior to reaching the DAC for waveform synthesis. Use of these DUCs is described in UG-1578.
The ADC front-end paths are all on the top of the platform and contain identical devices for all 16x RF input channels. These channels are comprised of filtering, two HMC8411 gain stages, gain control via a digital step attenuator (either the HMC425A for rev. A/B or HMC540S for rev. C), and a balun for single-ended to differential transitioning. Filtering can be swapped with footprint-compatible filters to access different Nyquist zones. The received signal is launched onto the board via an MMCX connector.
Once digitized via the ADC, the input signal can then be routed through the digital down converters (DDCs) of the AD9081 or AD9082 to reduce the data rate sampled by the ADCs and/or to frequency translate the data using either the fine or coarse numerically-controlled oscillators (NCOs). Use of these DDCs is described in UG-1578. Additionally, on-silicon programmable finite-impulse response filters (FIRs) can be used to achieve broadband equalization across the channels. The data then is sent over the JESD204b/c digital interface to the baseband processor (BBP).
Rev. A/B of the Quad-MxFE Platform uses the HMC425A as the receiver DSA for gain control. Rev. C of the Quad-MxFE Platform uses the HMC540S instead to provide a wider frequency coverage at the sacrifice of attenuation resolution. The DSA control is provided from both within ADI IIO Oscilloscope and via MATLAB control. The same DSA attenuation value is set for all ADC front-ends. Within ADI IIO Oscilloscope, the DSA value can be modified on the left side of the 'AD9081-3' tab as shown below. If using MATLAB to control the DSA value, then use the
A 500 MHz reference clock between 0-3dBm is required by the Quad-MxFE Evaluation Platform. The reference clock is provided via a vertical SMA female connector (reference designator J41) in the center of the board. From this reference clock, the on-board clock distribution network generates the sampling clocks and SYSREFs for the data converters, as well the FPGA clocks. The full clock generation tree for Rev. C of the Quad-MxFE Platform is shown below.
The quality of the clock directly impacts AC performance of the on-board data converters. Ensure that the external clock path remains clean of any power supply noise and select the phase noise and spur characteristics of the clock source to meet the target application requirements. To verify PLL lock, there is a blue LED connected to a lock detection output from each ADF4371 PLL synthesizer. A lit LED indicates that the PLL synthesizer associated with that channel has locked. The table below shows the mapping between the blue LEDs and MxFE channels.
|PLL/Synthesizer Lock Detect LEDs|
|MxFE#||PLL/Synthesizer Ref Des||LED Ref Des|
The Quad-MxFE Evaluation Platform also has provisions for directly driving the sampling clock of each MxFE data converter. An SMPM plug is available on each channel for this purpose, which connects to an AC-coupling capacitor that is not populated by default. Reference the schematic for more information. The table below lists the modifications required for direct clocking each channel.
|Direct Clocking Modifications|
|MxFE#||SMPM Ref Des||Modifications|
|0||J37||Depopulate C905, Populate C902|
|1||J38||Depopulate C955, Populate C952|
|2||J39||Depopulate C1005, Populate C1002|
|3||J40||Depopulate C1055, Populate C1052|
The AD9081 and AD9082 have on-chip PLLs to allow the user to inject a lower-frequency clock into the IC and then have this on-chip PLL generate the higher-frequency sample clock needed for the DACs/ADCs. Beginning with rev. C of the Quad-MxFE Platform, this capability is exposed with the use of differential HMC7043 outputs serving as this low-frequency clock source. To enable this capability, the user should perform the following default BOM platform modifications:
|On-Chip MxFE PLL Clocking Modifications (Rev. C Only)|
|0||Depopulate C886/C887, Populate C1118/C1119|
|1||Depopulate C936/937, Populate C1120/C1267|
|2||Depopulate C986/C987, Populate C1293/C1312|
|3||Depopulate C1036/C1037, Populate C1325/C1326|
Rev. A/B of the board does not implement length-matched SYSREFs. A goal of the platform's multi-chip synchronization (MCS) effort was to prove successful MCS functionality with non length-matched SYSREFs. MCS has been demonstrated on rev. A/B boards.
However, rev. C implements length-matched SYSREFs in an attempt to simplify software support going forward.
A greater detail of the SYSREF distribution is shown in the FPGA Clocks section.
The Quad-MxFE Platform operates by default in continuous SYSREF mode for rev. A/B of the system.
If desired, the HMC7043 can be operated in one-shot or N-shot SYSREF mode if using the HMC7043 in LVPECL output. However, the AD9081 devices require a LVDS input for its SYSREF. As such, an on-board LVPECL to LVDS transition is provided beginning with rev. C of the platform. This transition from LVPECL to LVDS is shown below.
For the Quad MxFE Rev B boards, there are a number of reference clocks that are routed back to the FPGA. In the Rev B design, there are a total of 5 clocks from the HMC7043 that are routed back to FPGA via the FMC+ adapter. The simple overview can be seen here:
Each of the reference clocks out of the HMC7043 shares the same architecture:
This architecture is such that each clock is normally terminated with 100Ω differential. Additional U.FL connectors can be included in the signal path by placing two DNI'd resistors on the board. An alternative star termination scheme can be used if the 49.9Ω to ground is populated. Each line is also AC coupled. These lines are fed to the FMC+ and then travel to the FPGA as shown. The text on each of the lines between items corresponds to the signal name in the schematic and the letter/number combos in the boxes references to the pin name/number on the FMC+ and the XCVU9P FPGA.
The simplified version of which signals are connected to which quads is seen here:
|Reference Clocks Rev B Board|
|Quad #||Quad Bank||MGTREFCLK0||MGTREFCLK1|
|121||X0Y2||HMC7043 CLKOUT2||HMC7043 CLKOUT0|
|122||X0Y3||HMC7043 CLKOUT4||HMC7043 CLKOUT0|
|125||X0Y6||HMC7043 CLKOUT6||HMC7043 CLKOUT0|
|126||X0Y7||HMC7043 CLKOUT2||HMC7043 CLKOUT0|
On the Rev C boards, the total number of reference clocks was cut down to 3. These are the FPGA REFCLK, FPGA JTX JESD and FPGA JRX JESD clocks from CLKOUT0/2/4 respectively. The HMC7043 also routes a number of SYSREF signals and other lower frequency clocks back to the FPGA as seen here:
Unlike in Rev B of the board, the three reference clocks to the FPGA have different circuits outside the HMC7043. The difference is the U.FL connectors which are not present on the FPGA JTX and JRX reference clocks:
The common architecture is such that each clock is normally terminated with 100Ω differential. An alternative star termination scheme can be used if the 49.9Ω to ground is populated. Each line is also AC coupled. These lines are fed to the FMC+ and then travel to the FPGA as shown. The text on each of the lines between items corresponds to the signal name in the schematic and the letter/number combos in the boxes references to the pin name/number on the FMC+ and the XCVU9P FPGA.
Note that the reference clocks for the JRX and JTX are not fed to a Quad PLL, but rather other clock inputs on the FPGA. The CLKOUT0 is the FPGA REFCLK and is fed to a number of Quad PLLs as seen here:
|Reference Clocks Rev C Board|
|Quad #||Quad Bank||MGTREFCLK0||MGTREFCLK1|
The Quad-MxFE Platform supports both JESD204b and JESD204c links. However, only four of the eight AD9081 SERDES lanes are routed on the board to the FMC+ connector, for a total of 16 SERDES lanes used in the system.
The following zip archive contains two excel spreadsheets that show the pinout of the Rev B and Rev C boards: fmc_pinout_vcu118_quadmxfe_revb_revc.zip
The AD9081 SPI interface is a 4-wire SPI by default, however the part can be run in a 3-wire interface is desired. There is a separate SPI bus for each of the AD9081s to allow for parallel operation if desired, but the FPGA currently supports sequential operation. The HMC7043 and ADF4371 are both wired for 3-wire SPI only. The ADF4371s share a common SPI bus with 4 CS lines. The HMC7043 has a separate dedicated SPI bus as well.
The EEPROM on the Quad MxFE board is a M24C02-RDW6TP which is a 2Kbit (256 byte) EEPROM with up an I2C interface speed up to 400kHz. In this design, the I2C SCL is run at 400kHz and the supply voltage is 3.3V from the VCU118 via the FMC+ connector. The address for this part is 101000b or 80 in decimal. This EEPROM is also queried by the VCU118 upon startup to determine the required VADJ level for the FMC+ VADJ. In the case the EEPROM is not programmed, the VADJ is automatically set to 1.8V.
On Rev C boards, the ADM1177 is used as a power monitor to measure the total current draw and voltage of the board.
The Quad-MxFE Evaluation Board develops all RF and digital rails from +12V through the 6-terminal Power Connector. The kit also includes a compatible AC adaptor. The Power Connector is a Molex 39301060 dual-row, right-angle header. The pinout is shown in the table below. Note that a 5A reverse polarity protection Schottky diode is connected between ground and +12V.
|Power Connector Pinout|
The on-board DC regulation scheme is shown below. The analog and mixed-signal voltage domains are largely generated from separate LDOs to keep them noise-isolated from one another.
They are broadly separated into these categories:
Since some of this circuitry is repeated, many of the voltage domains are further separated based on their corresponding MxFE channel.
A single 12V input is applied to the P1 connector, with a current rating greater than 8.8A. All voltages needed for the board are then derived from this source. Two LTM4633s, with downstream LDOs, help to provide the 1V rails for each MxFE. An LTM8053 helps to derive the 2V rails needed for each MxFE. The remaining 5V and 3.3V rails are ultimately derived from either an LTM8053 or an LTM8063, again with the aid of downstream LDOs.
1.8V_VADJ signal is also received by the Quad-MxFE Platform from the FPGA evaluation board and is used to power level translators and the
DVDD1P8 net on each MxFE to enable SPI communication.
Additionally, a 3.3V Power Good
PG_C2M signal is also received from the FPGA evaluation board (ie. the 'carrier') and is used to light the DS1 green LED and power the Quad-MxFE Platform (ie. the 'mezzanine') EEPROM to indicate proper operation and connectivity when connected to the FPGA board.
Beginning with Rev. B of the Quad-MxFE Platform, a dedicated LTM8063 (U121) was added with the sole intent to provide the 3.3V necessary to independently power the HMC7043 clock buffer IC.
The following LEDs should be lit during proper operation of the Quad-MxFE Platform. The LEDs are largely placed between the switching regulator uModules and the LDOs, so they often indicate an intermediate voltage prior to distribution downstream.
|Power LED Status Indicators|
|LED Ref Des||Function|
Beginning with Rev. C of the Quad-MxFE Platform, current and voltage monitoring is available via an ADM1177 I2C interface. Additionally, a 10A current limit threshold is set for the board and a voltage input threshold of greater than 10.4V is enabled.
Beginning with Rev. B of the Quad-MxFE Platform, the user is able to rotate ferrites prior to the LDOs on the board to investigate the system performance in which only the silent switcher μModules® are powering the downstream devices. Use this power distribution with caution, as this does require that the user also reprograms the μModule® output voltages using the external resistors near that part. The user can then determine if a power distribution system in which no LDOs are present fulfill the desired PSRR requirements for their design.
As an example for one LDO, notice that E14 and E15 share a common pad. E14 is normally populated, whereas E15 is set as 'Do Not Install' (DNI) by default. Also note that E15 is placed between the
1P3V_IN nets. The user can rotate the normally populated E14 to a position instead using E15, then modify the upstream μModule® voltage to output 1V instead of 1.3V, and then monitor a new power distribution topology.
Beginning with Rev. C of the Quad-MxFE Platform, a 12V power switch was installed to allow the platform to be plugged in to a wall or bench supply, but still switch power to the system.
Use of the Rev. A and B Quad-MxFE Platform requires an external fan blowing across the long direction of the platform during operation. This allows the board to maintain a thermal equilibrium and improves the JESD204b/c link signal integrity.
Beginning with Rev. C of the Quad-MxFE Platform, 5V 2-pin headers are placed near each AD9081 to power a heat sink and fan assembly which is mounted directly to each MxFE. This allows the thermal equilibrium of the platform to be maintained without the need of external fans.
Layout board files are provided to the customer after purchase of the Quad-MxFE Platform. These files have been developed using Cadence Allegro tools and are in the format of a .brd file. Detailed electromagnetic simulations were performed on the layout to ensure optimum RF performance in such a dense channel footprint.
A few highlights of the board layout include:
A full listing of the supported modes is located on the bottom half of this section here on software: Build descriptions and Download Link. As of July 2020, the following modes are supported:
The build files should be downloaded from this section Build descriptions and Download Link as well and unzipped to your desktop in a folder named QuadMxFE. As of July 2020, the following files are included in the download: The file naming convention is the following: