The Portable Radio Reference design is a combination of the ADRV9361-Z7035 RF SOM, a custom carrier board, custom and autogenerated HDL, the Linux kernel and userspace software to terminate the modem as /eth0. This combination provides an open source end to end reference design for hardware/software/hdl to form a complete datalink which can make a Linux TCP/IP connection.
The project includes MATLAB floating point simulations, Simulink floating point models, and HDL capable fixed-point models of a single carrier QPSK modem design. They also include integrations with SDR devices including PlutoSDR, FMCOMMS2/3/4, and ADRV-PACKRF for real-world testing.
All designs have been developed to communicate, over the air with one another and share a common testing harness for validation. Together, these designs demonstrate a true development cycle from simulation to hardware deployment. For deployment, which is completely untethered from MATLAB or Simulink, a specialized/custom reference design was created through ADI's board support package (BSP) and demonstrates a video link with the ADRV-PACKRF kit.
The custom carrier card inside the ADRV-PACKRF provides the user with connectors for additional hardware peripherals required for a hand held radio applications, such as sensors, power supplies, a real time clock and other analog functions. Several connectors are directly mounted to the carrier card and protrude from the face plate of the ADRV-PACKRF like Ethernet, micro SD, DC barrel jack, micro USB, and audio.
Additional headers on the carrier card provide connection to the OLED, navigation switch, IMU, ON/OFF push button and battery. These modules connect to the carrier card through various cables. The SOM connects to the carrier card through four 100 pin connectors. The SMA’s on the face plate of the box connect directly to the RF transceiver through a series of UFL to SMA cables.
The image above is a block diagram of the Portable Radio, detailing connections between the carrier card (including all connectors and peripheral modules) and the FPGA found on the RF SOM.
The primary objective of the power design is to generate a 5V, 5A (lots of headroom here) supply for the radio. Other goals include power source selection, hot swap management, battery charging maintenance and always on voltages.
Three individual power supply circuits are connected to a Power Source Selection device. This determines the appropriate power supply from which to power the radio.
The first input supply conforms to the 802.3at class 2 Power over Ethernet (POE+) standard. The LTC4269-1 high power PD (Powered Device) with integrated synchronous fly-back controller creates a 5V rail for powering the PCBs and peripherals. It handles all necessary handshaking to enable a connected class 2 (25.5W) or greater PoE Power Sourcing Equipment (PSE).
A class 2 PoE PSE is required to utilize this power source. The PSE used for all testing and demonstration is a Trendnet TPE-115GI Gigabit PoE+ injector. If the PackRF is connected to a non-POE capable Ethernet port, power will be drawn from the external wall wart or the internal battery.
One challenge encountered in designing, testing and using the LTC4269 deals with converter start up. In operation, the trickle charge resistor, RTR, is connected to VIN and supplies a small current, typically on the order of 1mA to charge CTR. Initially the LTC4269-1 is off and draws only its start-up current. When CTR reaches the VCC turn-on threshold voltage the LTC4269-1 turns on abruptly and draws its normal supply current. Switching action commences and the converter begins to deliver power to the output. Initially the output voltage is low and the ﬂyback voltage is also low, so CTR supplies most of the LTC4269-1 current (only a fraction comes from RTR.) VCC voltage continues to drop until, after some time (typically tens of milliseconds) the output voltage approaches its desired value. The ﬂyback winding then provides the LTC4269-1 supply current and the VCC voltage stabilizes.
If CTR is undersized, VCC reaches the VCC turn-off threshold before stabilization and the LTC4269-1 turns off. The VCC node then begins to charge back up via RTR to the turn-on threshold, where the part again turns on. Depending upon the circuit, this may result in either several on-off cycles before proper operation is reached, or permanent relaxation oscillation at the VCC node.
Make CTR large enough to avoid the relaxation oscillatory behavior described above. This is complicated to determine theoretically as it depends on the particulars of the secondary circuit and load behavior. Empirical testing is recommended and was performed on two separate occasions as changes in layout necessitated resizing CTR.
The external DC power supply input is a 5.5mm barrel jack, which works with the wide input voltage range of the LTC3899 (4.5 to 60V) allowing the radio to be powered from a multitude of external supplies including:
Not all barrel jacks are the same. The ADRV-PACKRF requires a positive center conductor, with a 2.1mm inner diameter and 5.5mm outer diameter. DOUBLE CHECK – most AC/DC wall adapters have center positive polarity, but some have center negative / barrel positive polarity.
Each PackRF comes with a pair of automotive power plug to DC Cigarette lighter adapters for the engineer on the go. Many new automobiles are including an automated start-stop system that turn the engine off at red lights or traffic jams, to meet increased fuel economy metrics. As the engine is restarted, the starter motor cold cranks the battery to start the engine. For safety, the power management system must not droop any supplies during these sorts of stop-start events, where very low voltages (~3V) can be seen for 10-100ms.
Load dump is a similar issue. The voltage surge produced by an automotive alternator when the battery or some other significant load is accidentally disconnected can temporarily be as high as 60V in a nominal 12V vehicle. All electronics connected to the automotive supplies need to withstand these sorts of voltages.
The third supply is an internal lithium-ion battery backup. The ADP1621 step-up DC to DC controller regulates the battery voltage (3.7V typical) to create an emergency supply. At 3200mAh, the battery is only capable of powering the system for a limited time. Heavy loads on the FPGA reduce the 'back-up' operating time to under 1 hour, but that time depends entirely on system utilization and how much power is being consumed. The battery has a built-in protection circuit to detect over-charge, over-drain, short circuit and over-temperature conditions to protect the battery (and system) from damage.
Battery charging is overseen by the ADP5061 allowing the user to set and modify certain critical variables, including, but not limited to:
This ensures that the battery is charged safely and consistently.
The system will charge the battery when it is powered down, but it does require power to be applied to the unit. Either POE or the wall wart must be plugged into the radio. These voltages do not require validation from the LTC4417 power source selector. The LTC4415 diode OR’s these voltages to create a 'supply' voltage for the ADP5061 battery charger IC.
The LTC4417 power source selector output voltage (+5V) is not used to power the battery charge IC because this would require the unit to be turned on to enable battery charging.
Preservation of battery charge is critical for all electronics. Excess current draw must be avoided in all forms. When the battery is not generating 5.0V, there is a path through the diode, from ‘+V_Batt’ to ‘+5V_Batt’. This means any load on that net (resistor dividers, IC’s diodes etc.), dissipates battery life. Placing a high current rating transistor in the current path, allows a control signal to drive the gate and disconnect the current path from any load. This minimizes load on the battery when the switcher is off.
The system selects between three input power sources; Power over Ethernet (V1), DC Supply (V2), battery(V3). The LTC4417 Power Path Selector prioritizes the inputs as V1, V2, V3. If V1 is valid it is the input used to power the system (will call this V_PCB). If V1 invalid, V2 is used. If V2 invalid, V3 is used. If V3 invalid, then the system is off.
The LTC4417 validates each input by comparing it to an under voltage threshold (UV) and over voltage threshold (OV). The voltage must remain inside the window for 256 ms or it is considered invalid and the timer resets.
As an example, two resistor dividers are connected to the 5V rail created by the external supply (+5V_EXT). One divides the input voltage down for comparison against the under voltage threshold(1V), the sother for comparison against the over voltage threshold(1V). If both of these conditions are met, the supply is valid, and the IC drives the transistor gates to connect the voltage to all downstream circuitry.
The moment the UV1 or OV1 threshold is triggered (and V2 is valid) the gate drive pins of the transistors change. There is a 3 uS break-before-make time to protect the power supplies from feeding back through the transistors. The entire process takes less than a generous 75 uS, while maintaining a 4A load maximum. In reality it is much closer to 10 uS.
There are roughly four stages of importance when considering the hot swap.
Now to tackle the numbers. How do we decide on UV and OV thresholds? It is actually the ADRV9361-Z7035 which dictates the decision. The input voltage range for the SOM is strictly set at 4.5V to 5.5V. This was carefully designed as to protect the FPGA from damage. When the OV or UV is triggered, the system must switch to the next power supply before the capacitor bank runs out of charge and the voltage droops beyond the 4.5V.
There are two factors at play here. The first is, if you make the window around 5V too wide, you leave very little headroom to respect the 4.5V-5.5V. Ultimately, this would trigger protection circuitry on the SOM and it would shut down anyway, but we design for this regardless. Alternatively, if you make the window around 5V too narrow, normal voltage transients could trigger a fault.
So now we have the following
Most of the time, the system is not consuming 4 amps. A significant amount of headroom was included so the capacitance can be reduced according to the calculated load of the system. 1.5mF is a very large capacitance, particularly when it needs to be distributed around the PCB. Charge is needed in many locations, not just at a single point. So to stack all the capacitance somewhere, or in one component is insufficient. The balance can be tricky between having enough capacitance to guarantee operation, and having too much capacitance where it influences the performance of the switching regulators. Excessive capacitance can cause the switchers problems in start up, or even destabilize the converter and shut it down.
A few empty pads are included to allow modification of the net capacitance in case of temperature, voltage de-rating etc.
An issue exists where the capacitor bank used to maintain the 5V supply during hot swap actually causes a problem on shutdown. When shutting down, the IC waits for the output voltage to drop below a certain threshold before it can power up again. The large capacitor bank performs its function a little too well in that it keeps the 5V rail high for seconds, as opposed to the desired micro or milliseconds. The image below depicts the output voltage (blue line) on an early revision of the PCB, with the yellow line being the input supply voltage (ironically this image depicts a second problem in the initial PCB but that is for another section.)
The system is very clearly turned off where the blue line drops vertically. Approximately three seconds later, someone tries to restart the system but the output voltage has yet to fall sufficiently. The system does not turn on and the user is left scratching their head.
A PMOS transistor is added to expedite this discharge. When 'System_Enable' goes low (as a result of power fault, kill signal asserted, push button etc), the transistor shorts the 5V rail to ground.
Just having a push button to enable/disable the radio is insufficient. When the unit is off, there needs to be power for the push button IC (and a few other very low power items) so it can be turned on. The raw battery voltage allows a small, low power circuit to always be powered. The power consumed by this circuit will have little to no impact on battery charge. When the system is functioning, either the POE or External power will take over from the battery.
The radios are designed to operate in a similar manner to a laptop.
Assume the following:
A user tries to turn the unit on. This drives 'SYSTEM_ENABLE' high which activates a high side switch. This switch is required to invert the gate drive and close the transistor so it can conduct current. The ADP1621 begins to try and boost the battery voltage to '+5V_BATT'.
The problem is one of timing. The LTC2955 'KILL_N' signal acts to shut the system down when driven low. Put alternatively, something(the pull up resistor) has to pull this net high. There is a blanking period in which this signal is ignored. This means, once the enable output is asserted, you have 304ms to 720ms (512ms typical) for 'KILL_N' to go high, or the system will shut down.
Note: the POE and external supply do not run into this problem because they are validated by the LTC4417 before the enable is pushed. It is because of the added gating transistor to the battery circuit that we have this extra delay.
720ms… that is a long time! Why is this a problem?? The LTC4417 validation time is 100ms to 412ms. So, once the ADP1621 regulates the battery voltage to create '+5V_BATT', the LTC4417 can take anywhere from 100ms to 412ms to confirm this voltage is ready for use in the rest of the system. Unfortunately, 412ms is longer than 304ms, and this does not include additional constraints:
So in the worst case, the system won't start up because of this unfortunate race condition. One solution is to change the pull-up resistor voltage to '5V0_Always_On'. This way, we only utilize the kill function when the FPGA drives the net low.
Unfortunately this creates another problem, you have a signal driving the FPGA before the FPGA is on. This can cause damage to the FPGA and essentially 'brick' the radio. A simple level translator solves the problem.
The Zynq PS includes a 10/100/1000 hardened Ethernet MAC port using a Marvell 88E1512 PHY. A unique MACID for this port is provided with each SOM as a printed label on the module. It must be manually entered in Linux or included in the boot files for Zynq.
The Marvell PHY operates at 1.8V. The PHY connects to Zynq PS MIO Bank 1/501 (1.8V) with an RGMII interface. The PHY reset connects to Zynq PS MIO Bank 0/500.
The AD9361-Z7035 module does not include the RJ-45 interface. The signals are connected to the JX3 micro header receptacle. The magnetics and RJ-45 jack are located on the carrier card. The image below shows the major connections pertaining to the ethernet PHY.
The Radio uses one of the hardened USB 2.0 high speed controllers with on-the-go (OTG) dual role USB host controller or USB device controller. The AD9361-Z7035 uses this Zynq PS peripherals, in combination with a USB2.0 UTMI+ low pin interface (ULPI) PHY device, to provide USB 2.0 OTG signaling to the JX3 connector.
The LTC2942 measures battery voltage and chip temperature. A precision coulomb counter integrates current through a sense resistor between the battery’s positive terminal and the load or charger. Battery voltage and on-chip temperature are measured with an internal 14-bit No Latency ∆∑™ ADC. The three measured quantities (charge, voltage and temperature) are stored in internal registers accessible via the onboard SMBus/I2C interface.
The coulomb counter is used to approximate the voltage and charge remaining inside the battery, so it can be displayed in the menu.
* The ADIS16460 is a complete inertial system that includes a tri-axial gyroscope and a tri-axial accelerometer.
Many of the devices found on both the carrier and daughter card are accessible through I2C. Care has been taken to check voltage levels and addresses for all devices. Translation has been included in both domains ensuring a safe, reliable system. The image below does not include the voltage translators for each I2C connection requiring one. Instead, the voltage is listed and have faith that they exist in the design!
The I2C address translator was included in the image as it is more unusual. The Real Time Clock shares an address with the ADM1166 found on the daughter card. A simple translation bit allows us to differentiate between the devices and maintain communications.
The I2C connection is found on JX2, pins 17 and 19. This is common between the ADR936x designs of this form factor.