These low power ADCs offer very high performance from 14-bits up to 18-bits with throughputs ranging from 100ksps to 1.3MSPS. The boards are designed to demonstrate the ADC's performance and to provide an easy digital interface for a variety of system applications. A full description of these products are available in their respective data sheets and should be consulted when utilizing the boards. To purchase hardware, please visit our website.
In the ADI Reference Designs HDL User Guide can be found an in-depth presentation and instructions about the HDL design in general.
The reference design uses the standard SPI Engine Framework with an integrated pwm generator, which will provide the required conversion rate for the ADC.
Steps for building the HDL design:
The reference design uses a clock generator for the divison of the spi clock and a pwm generator for the conversion signal. The required parameters can be set in https://github.com/analogdevicesinc/hdl/blob/master/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl file using the following values, where the PULSE_0_PERIOD is computed as Tcyc_min/Tspi_clk: