This version (19 Nov 2021 13:10) was approved by Stanca-Florina Pop.



These low power ADCs offer very high performance from 14-bits up to 18-bits with throughputs ranging from 100ksps to 1.3MSPS. The boards are designed to demonstrate the ADC's performance and to provide an easy digital interface for a variety of system applications. A full description of these products are available in their respective data sheets and should be consulted when utilizing the boards. To purchase hardware, please visit our website.


  • Battery-powered equipment
  • Data acquisition
  • Instrumentation
  • Medical instruments
  • Process controls

Supported Devices

Evaluation Boards

HDL Design Description

In the ADI Reference Designs HDL User Guide can be found an in-depth presentation and instructions about the HDL design in general.

The reference design uses the standard SPI Engine Framework with an integrated pwm generator, which will provide the required conversion rate for the ADC.

HDL Block Diagram

Steps for building the HDL design:

  1. Confirm that you have the right tools (the reference design requires Vivado 2021.1)
  2. Clone the HDL GitHub repository (the project is located at pulsar_adc_pmdz)
  3. Set up the required sampling rate (see caption Design Configuration)

Design Configuration

The reference design uses a clock generator for the divison of the spi clock and a pwm generator for the conversion signal. The required parameters can be set in file using the following values, where the PULSE_0_PERIOD is computed as Tcyc_min/Tspi_clk:

AD7942 640
AD7946 320
AD7988-1 1600
AD7685 640
AD7687 640
AD7691 640
AD7686 320
AD7688 320
AD7693 320
AD7988-1 320
AD7980 160
AD7983 120
AD7690 250
AD7982 160
AD7984 120

HW Platform(s):

HDL Downloads

resources/eval/user-guides/pulsar_adc_pmods_hdl.txt · Last modified: 16 Nov 2021 16:12 by Stanca-Florina Pop