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resources:eval:user-guides:pioneer1-wiredcbm [14 Aug 2019 16:39]
Richard Anslow
resources:eval:user-guides:pioneer1-wiredcbm [16 Feb 2021 10:34]
Richard Anslow
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   * Typical SPI SCLK rate vs. cable length performance in a Phantom Power network is characterized in Figure 2. This shows  DEMO-CbM-Slave3-Z (non-isolated slave) and DEMO-CbM-Slave2-Z (isolated slave)error free performance when  porting the ADcmXL3021 SPI output over cabling. ​   * Typical SPI SCLK rate vs. cable length performance in a Phantom Power network is characterized in Figure 2. This shows  DEMO-CbM-Slave3-Z (non-isolated slave) and DEMO-CbM-Slave2-Z (isolated slave)error free performance when  porting the ADcmXL3021 SPI output over cabling. ​
  
-{{:​resources:​eval:​user-guides:​pioneer_1_kit_sclk_vs_dr_wiki1.png|}}+{{ :​resources:​eval:​user-guides:​pioneer_1_kit_sclk_vs_dr_wiki_rev1.png?600 |}}
  
 **Figure 2. SPI SCLK vs. Cable Length Typical Performance** **Figure 2. SPI SCLK vs. Cable Length Typical Performance**
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 Schematics, layout, BOM, and Gerber file for the DEMO-CbM-Expandr-Z:​ Schematics, layout, BOM, and Gerber file for the DEMO-CbM-Expandr-Z:​
 {{ :​resources:​eval:​user-guides:​demo-cbm-expandr-z_zip.zip |click here to download}} {{ :​resources:​eval:​user-guides:​demo-cbm-expandr-z_zip.zip |click here to download}}
 +
 +===== LTspice Simulation =====
 +A simplified power over data wires simulation circuit is provided in Figure 10. This circuit uses LTC2862 RS-485 transceiver LTspice macromodels and 1 mH inductors (Wurth 74477830). LTspice includes real inductor models, which include device parasitics, enabling closer correlation between simulation and real design performance. The DC blocking capacitor values are 10 µF. In general, using larger inductor and capacitor values enable a lower data rate performance on the communication network. The simulated test case is a 250 kHz data rate, which roughly corresponds to 100 meters of cabled communication when porting clock synchronised SPI over an RS-485 interface. The input voltage waveform used in the simulation corresponds to a worst-case dc content, with a 16-bit word and all logic high bits. Simulation results are presented in Figures 11 and 12. The input voltage waveform (VIN) matches the output at the remote powered device (no communication errors). Figure 12 presents a zoomed-in view of the bus voltage differential waveform (voltage A – voltage B) for droop analysis. The voltage at the remote sensor node, extracted from the L2 inductor (V(pout)) provides a power supply rail of 5V±1mV.
 +
 +{{ :​resources:​eval:​user-guides:​new.png |}}
 +**Figure 10. Engineered Power LTspice simulation circuit using LTC2862 (RS-485) and 1mH Wurth Inductor 74477830**
 +
 +{{ :​resources:​eval:​user-guides:​11.png |}}
 +**Figure 11. Simulation Result with RS-485 bus differential voltage V(A,B) , and droop points X and Y**
 +
 +{{ :​resources:​eval:​user-guides:​12.png |}}
 +**Figure 12. Droop analysis for point X and Y**
 +
 +{{ :​resources:​eval:​user-guides:​13.png |}}
 +
 +The VDROOP, VPEAK, and TDROOP are measured using the Figure 11 and 12 LTspice waveform. The L and C values are then calculated using equations 2 and 4. It depends where you measure on the waveform, however, the calculated L value is 1 to 3mH as shown in Table 1. Measuring at point X (Figure 12) is most accurate and yields the correct inductance value of approximately 1 mH. The high pass filter frequency (equation 6) is simply a function of the droop time and voltage, and for point X is approximately equates to 250 kHz/32 for 1 bit (half clock cycle), which matches the input waveform (V3) shown in the Figure 10 schematic.
 +
 +**Table 1**
 +{{ :​resources:​eval:​user-guides:​table.png |}}
 +
 +When simulating Figure 10 it is also worth noting that the C8 capacitor is recommended to reduce voltage overshoot at the sensor (Vpout at power extraction node). With C8 added the overshoot is maximum 47mV and settles to within 1mV of the desired 5VDC within 1.6ms. Simulating without a C8 capacitor results in an underdamped system, with 600mV overshoot, and a permanent 100mV of voltage oscillation from the 5V dc target.
 +
 +LTSpice models are available here:
 +{{ :​resources:​eval:​user-guides:​podl_article.zip |click here to download}}
  
 ===== Change Log ===== ===== Change Log =====
  
-July 2019. Initial Release+*July 2019. Initial Release
 + 
 +*August 2019. Added additional information on demo power supply configuration.
  
 +*February 2021. Added LTspice models for engineered power.
  
  
resources/eval/user-guides/pioneer1-wiredcbm.txt · Last modified: 16 Feb 2021 10:34 by Richard Anslow