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resources:eval:user-guides:mykonos:reference_hdl [22 Feb 2017 19:26] – Canonical spelling of JESD204B Lars-Peter Clausenresources:eval:user-guides:mykonos:reference_hdl [16 Mar 2018 09:52] – Update the block design, no PRBS in the core Istvan Csomortani
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 The HDL reference design is an embedded system built around a processor core either ARM, NIOS-II or Microblaze. A functional block diagram of the system is shown below. The device digital interface is handled by the transceiver IP followed by the JESD204B and device specific cores. The JESD204B lanes are shared among the 4 transmit, 4 receive and 2 observation/sniffer receive data paths by the same set of transceivers within the IP. The cores are programmable through an AXI-lite interface. The delineated data is then passed on to independent DMA cores for the transmit, receive and observation/sniffer paths. The HDL reference design is an embedded system built around a processor core either ARM, NIOS-II or Microblaze. A functional block diagram of the system is shown below. The device digital interface is handled by the transceiver IP followed by the JESD204B and device specific cores. The JESD204B lanes are shared among the 4 transmit, 4 receive and 2 observation/sniffer receive data paths by the same set of transceivers within the IP. The cores are programmable through an AXI-lite interface. The delineated data is then passed on to independent DMA cores for the transmit, receive and observation/sniffer paths.
  
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 ===== Digital Interface ===== ===== Digital Interface =====
  
resources/eval/user-guides/mykonos/reference_hdl.txt · Last modified: 06 Jun 2018 13:33 by Adrian Costina