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AD9371/AD9375 No-OS Setup

Xilinx Platform

This guide provides some quick instructions on how to setup the AD9371 mykonos on:

Required Software

  • We're upgrade the Xilinx tools on every release. The supported version number can be found in our git repository .
  • Open Xilinx Software Development Kit (XSDK) and provide the workspace location.
  • Create a new Application Project: go to File → New → Application Project

Creating a new application project

  • Create a new Hardware Platform: click New from the Target Hardware section

Creating a new hardware platform

Import hardware description file

  • Give a name to the project and to the board support package and click Next

Application project settings

  • Select the Empty Application templeta and click Finish

Choose application template

  • The new Empty Application project should look like:

Empty application project

Some applications (e.g. FMCOMMSx), when a Microblaze processor is used, requires an increased HEAP size for dynamic memory allocation. Make sure the HEAP size is at least 0x100000.

  • Copy the source code files into the src directory
  • If there are multiple folders present in in the src one, include all the paths of the folders: go to the settings of the project and in the C/C++ Build → Settings → Tool Settings → gcc compiler → Directories section and add the paths of all the folders.
  • The SDK should automatically build the projects and the Console window will display the result of the build. If the build is not done automatically select the Project → Build Automatically menu option.
  • At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. You can program the FPGA by clicking on Xilinx Tools → Program FPGA
  • After the FPGA was programmed, we need to create a new Run configuration, by selecting RunRun Configurations…, in the Run Configuration windows select the Xilinx C/C++ application (GDB) and click at the New Configuration button at the upper left corner.

Create new run configuration

  • If your target carrier has a Zync SoC, make sure, that you specify the Initialization file, and select the Run ps7_init and Run ps7_post_config options.

Define Zynq initialization file

  • At the Application tab define your current project name and application executable. (.elf)
  • The output of the example program can be viewed in the SDK console by enabling the Connect STDIO Console option and setting the baud rate of the UART port to 115200.

Define Zynq initialization file

  • As an alternative a UART terminal can be used to capture the output of the example program. The number of used UART port depends on the computer's configuration. The following settings must be used in the UART terminal:
  • Baud Rate: 115200bps
  • Data: 8 bit
  • Parity: None
  • Stop bits: 1 bit
  • Flow Control: none
  • When the run configuration is done, the software can be started by clicking the Run button.
  • Your new bare metal application should run
27 Feb 2015 14:57 · CsomI

Files

  • API Source Code
    • Unzip the archive and go into src→api folder
    • Next copy the ad9528 and mykonos folder to the src folder of your project. Do NOT copy the common.c and common.h files provided by the api. For now, use the ones downloaded from github.
    • Make sure the paths for the directories are included. Right click on the src folder from Project Explorer and go to Properties → C/C++ Build → Settings → ARM v7 gcc compiler → Directories

  • Click Add → Workspace… →ad9528

  • Repeat the procedure for mykonos, src and mykonos_debug. The included paths should look like this:

  • Add the above folders also for Configuration: Debug

  • Transceiver Evaluation Software
    • Next, generate the profile by using the MATLAB Profile Generator. The profiles can be used with the Transceiver Evaluation Software to evaluate system performance.
    • Further, import the profile into TES, and generate the Mykonos initialization structures which are used by the No-OS driver (Tools → Create Script → C Script). Follow the AD9370 Quick Start Guide.pdf from AD9371 Transceiver Evaluation Software\Resources folder.
    • The script generates headless.c, headless.h, myk.c, myk.h and myk_ad9528init.c files. Add myk.c, myk.h and myk_ad9528init.c to the src folder of your project. Do NOT add headless.c and headless.h, instead use the files provided in github.
    • The build should return no error and Project Explorer should look like this:

  • Note: The AD9371/AD9375 evaluation board contains an on-board voltage controlled crystal oscillator (VCXO), there are limitations with the default hardware configuration in the scenario where user desired device frequencies are not related to the on-board 122.88 MHz VCXO by a rational fraction.

Push data into/out of the AD9371/AD9375

Below is defined the dac_core structures used by the dac_setup() and dac_write_custom_data() functions:

	typedef struct
	{
		uint32_t base_address;
		uint8_t	 resolution;
		dac_channel *channels;
		uint32_t dac_ddr_baseaddr;
	}dac_core;
 
	typedef struct
	{
		uint32_t dds_frequency_tone0;       // in hz (1000*1000 for MHz);
		uint32_t dds_phase_tone0;           // in milli(?) angles (90*1000 for 90 degrees = pi/2)
		int32_t dds_scale_tone0;            // in micro units (1.0*1000*1000 is 1.0)
		uint32_t dds_frequency_tone1;       // in hz (1000*1000 for MHz)
	        uint32_t dds_phase_tone1;           // in milli(?) angles (90*1000 for 90 degrees = pi/2)
	        int32_t dds_scale_tone1;            // in micro units (1.0*1000*1000 is 1.0)
	        uint32_t dds_dual_tone;         // if using single tone for this channel, set to 0x0
	        uint32_t pat_data;              // if using SED/debug that sort of thing
	        dac_data_src sel;               // set to one of the enumerated type above.
	}dac_channel;

Below is defined the adc_core structure used by the adc_setup() and adc_capture() functions:

	typedef struct
	{
		uint32_t base_address;
	        uint8_t	 master;
	        uint8_t	 no_of_channels;
	        uint8_t	 resolution;
	        uint32_t start_address;
	}adc_core;

DDS Mode

  • Set dac_data_src to DAC_SRC_DDS and configure dac_core and dac_channel with the desired options.

DMA Mode

  • Set dac_data_src to DAC_SRC_DMA.
  • dac_write_custom_data() function takes as argument the sine_lut_iq array which contains the custom data to be transmitted.
  • The format for each I and Q is 16-bit signed two's complement. I and Q together make up one 32-bit tx sample.

Capture data

  • Once DDS or DMA mode is selected and the project configuration can be ran.
  • Open an UART terminal, set the baud rate to 115200bps and make sure the initialization was completed, as in the screenshot bellow:

  • Next, download the capture scripts from the git repository.
  • capture.bat script contains the path of the Xilinx SDK, the default is “C:\Xilinx\SDK\$VERSION”; if on your PC the path is different, you need to update it according to your project setup.
  • By running capture.bat, the iq_rx1.csv and iq_rx2.csv files will be generated.
  • Start VisualAnalog and open the visual_analog.vac file downloaded from the git repository.
  • From the Pattern Loader window, browse for the newly generated .csv files and click Run. The result should look something like in the screenshot below:

Intel/Altera Platform

This guide provides some quick instructions on how to setup the AD9371 mykonos on:

Required Software

Altera Software setup

This section is intended to give a briefly review about how the user can make a new application project for his or her hdl design. If you are an advanced user, you probably want to skip this section.

Before the image can be loaded the Quartus Prime 16.0 tool or the Quartus Prime 16.0 Programmer must be installed on your computer.

  • The first step before get started is to build the desired HDL design.
  • Open the NIOS II Software Build Tools for Eclipse. When NIOS II starts it asks to provide a folder, where to store the work space. Any folder can be provided.
  • Go to File → New → NIOS II Board Support Package
  • Browse for the SOPC Information File:
  • Type a Project name and click Finish:
  • Go to File → New → NIOS II Application
  • Select the BSP location, type a Project name and click Finish
  • The brand new NIOS II Application should look like:
  • The next step is to copy all the relevant source code into the software directory.
  • AD9371/AD9375 No-OS Software
  • Transceiver Evaluation Software
    • Next, generate the profile by using the MATLAB Profile Generator. The profiles can be used with the Transceiver Evaluation Software to evaluate system performance.
    • Further, import the profile into TES, and generate the Mykonos initialization structures which are used by the No-OS driver (Tools → Create Script → C Script). Follow the AD9370 Quick Start Guide.pdf from AD9371 Transceiver Evaluation Software\Resources folder.
    • The script generates headless.c, headless.h, myk.c, myk.h and myk_ad9528init.c files. Add myk.c, myk.h and myk_ad9528init.c to the src folder of your project. Do NOT add headless.c and headless.h, instead use the files provided in github.
    • Note: The AD9371/AD9375 evaluation board contains an on-board voltage controlled crystal oscillator (VCXO), there are limitations with the default hardware configuration in the scenario where user desired device frequencies are not related to the on-board 122.88 MHz VCXO by a rational fraction.
  • Nios II Eclipse should automatically build the projects and the Console window will display the result of the build. If the build is not done automatically select the ProjectBuild Automatically menu option.
  • Note: if you get this error: warning: Unable to reach (null) (at 0x00088608) from the global pointer (at 0x000752b8) because the offset (78672) is out of the allowed range, -32678 to 32767, a quick workaround can be found on the Altera support page: modify the linker.x file from your bsp by deleting + SIZEOF (.rwdata) from this one line:
  • At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. You can program the FPGA by using Quartus Prime Programmer. Load your .sof file and click Start, the Progress bar should indicate 100% (Successful)
  • Next, go to Nios II eclipse and select Run → Run Configurations…
  • Select the Nios II Hardware configuration type.
  • Press the New button to create a new configuration.
  • On the Target Connection tab, press the Refresh Connections button. You may need to expand the window or scroll to the right to see this button.
  • Check the Ignore mismatched system ID option.
  • Check the Ignore mismatched system timestamp option.
  • Press the Run button in the Run Configurations window.
  • This will re-build the software project to create an up–to-date executable and then download the code into memory.

Push data into/out of the AD9371/AD9375

Below is defined the dac_core structures used by the dac_setup() and dac_write_custom_data() functions:

	typedef struct
	{
		uint32_t base_address;
		uint8_t	 resolution;
		dac_channel *channels;
		uint32_t dac_ddr_baseaddr;
	}dac_core;
 
	typedef struct
	{
		uint32_t dds_frequency_tone0;       // in hz (1000*1000 for MHz);
		uint32_t dds_phase_tone0;           // in milli(?) angles (90*1000 for 90 degrees = pi/2)
		int32_t dds_scale_tone0;            // in micro units (1.0*1000*1000 is 1.0)
		uint32_t dds_frequency_tone1;       // in hz (1000*1000 for MHz)
	        uint32_t dds_phase_tone1;           // in milli(?) angles (90*1000 for 90 degrees = pi/2)
	        int32_t dds_scale_tone1;            // in micro units (1.0*1000*1000 is 1.0)
	        uint32_t dds_dual_tone;         // if using single tone for this channel, set to 0x0
	        uint32_t pat_data;              // if using SED/debug that sort of thing
	        dac_data_src sel;               // set to one of the enumerated type above.
	}dac_channel;

Below is defined the adc_core structure used by the adc_setup() and adc_capture() functions:

	typedef struct
	{
		uint32_t base_address;
	        uint8_t	 master;
	        uint8_t	 no_of_channels;
	        uint8_t	 resolution;
	        uint32_t start_address;
	}adc_core;

DDS Mode

  • Set dac_data_src to DAC_SRC_DDS and configure dac_core and dac_channel with the desired options.

DMA Mode

  • Set dac_data_src to DAC_SRC_DMA.
  • dac_write_custom_data() function takes as argument the sine_lut_iq array which contains the custom data to be transmitted.
  • The format for each I and Q is 16-bit signed two's complement. I and Q together make up one 32-bit tx sample.

Capture data

  • Once DDS or DMA mode is selected and the project configuration can be ran.
  • Open an UART terminal, set the baud rate to 115200bps and make sure the initialization was completed, as in the screenshot bellow:
  • Next, download the capture scripts from the git repository.
  • By running capture.bat, the iq_rx1.csv and iq_rx2.csv files will be generated inside the nios2eds folder
  • Start VisualAnalog and open the visual_analog.vac file downloaded from the git repository.
  • From the Pattern Loader window, browse for the newly generated .csv files and click Run.

Download no-OS

The source code of the no-OS software and the scripts can be downloaded from the Analog Devices github.

resources/eval/user-guides/mykonos/no-os-setup.txt · Last modified: 18 Jan 2019 16:44 by DragosB