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resources:eval:user-guides:interface-isolation:eval-ltc4317-pmdz [26 Jan 2022 18:51] – [IMPORTANT NOTES] Naveen Afzalresources:eval:user-guides:interface-isolation:eval-ltc4317-pmdz [26 Jan 2022 18:56] (current) – [GETTING STARTED] Naveen Afzal
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   - Power up the upstream side of the board and the [[adi>LTC4317|LTC4317]] via the P1.6 pin. Connect P1.5 to GND and P1.4 and P1.3 to SDA and SCL of the host controller respectively. If the host controller is available in a PMOD form factor, plug in the P1 PMOD connector into the six pin PMOD host connector of the controller.   - Power up the upstream side of the board and the [[adi>LTC4317|LTC4317]] via the P1.6 pin. Connect P1.5 to GND and P1.4 and P1.3 to SDA and SCL of the host controller respectively. If the host controller is available in a PMOD form factor, plug in the P1 PMOD connector into the six pin PMOD host connector of the controller.
   - Power up the downstream buses 1-2 using separate power supplies or from the upstream side. To power all the buses using the upstream voltage supply, place the jumpers JP1 in A and B positions. This will connect VCCIN to the VCC1-VCC2 of the downstream buses.   - Power up the downstream buses 1-2 using separate power supplies or from the upstream side. To power all the buses using the upstream voltage supply, place the jumpers JP1 in A and B positions. This will connect VCCIN to the VCC1-VCC2 of the downstream buses.
-  - Configure the resistors, RLTx, RLBx, RHTx and RHBx to set the desired translation byte for the downstream buses, Busx on the [[adi>en/products/ltc4317.html|LTC4317]]. By default, the translation byte for Bus 1 is hardwired to '0000001' and the translation byte for Bus 2 is hardwired to '0000010' on the EVAL-LTC4317-PMDZRefer to Table 1, Table 2 and Table 3 on the datasheet. The voltages at the XORH and XORL pins configure the translation byte. The XORL voltage configures the lower 4 translation bits (excluding the R/W bit), while the XORH voltage configures the upper 3 translation bits. Tables 2 and 3 on the datasheet show the recommended resistive divider values. RLT and RLB are the top and bottom resistors connected to XORL, while RHT and RHB are the top and bottom resistors connected to XORH.+  - Configure the resistors, RLTx, RLBx, RHTx and RHBx to set the desired translation byte for the downstream buses, Busx on the [[adi>en/products/ltc4317.html|LTC4317]]. By default, the translation byte for Bus 1 is hardwired to '0000001' and the translation byte for Bus 2 is hardwired to '0000010' on the EVAL-LTC4317-PMDZ (Refer to Table 1, Table 2 and Table 3 on the datasheet for more information on how to change the Address Translation Byte). The voltages at the XORH and XORL pins configure the translation byte. The XORL voltage configures the lower 4 translation bits (excluding the R/W bit), while the XORH voltage configures the upper 3 translation bits. Tables 2 and 3 on the datasheet show the recommended resistive divider values. RLT and RLB are the top and bottom resistors connected to XORL, while RHT and RHB are the top and bottom resistors connected to XORH.
   - Slaves can be connected to two different buses for two Independent Address Translations (using two different Translation Bytes that can be set using XORH1, XORL1 and XORH2 and XORH2 pins) or connected to one bus, sharing one channel. In this configuration, they will have their input addresses XORed with the same translation Byte using either set of pins (e.g. XORH1, XORL1 or XORH2 or XORL2).   - Slaves can be connected to two different buses for two Independent Address Translations (using two different Translation Bytes that can be set using XORH1, XORL1 and XORH2 and XORH2 pins) or connected to one bus, sharing one channel. In this configuration, they will have their input addresses XORed with the same translation Byte using either set of pins (e.g. XORH1, XORL1 or XORH2 or XORL2).
-  - If the master wants to communicate with the slave using the general call address, it can temporarily disable address translation by pulling XORH high. This disables address translation and keeps N1 and N2 on regardless of the activity on the buses, turning on the pass through mode (N1 connects SCLIN to SCLOUT while N2 connects SDAIN to SDAOUT).  Any translation that may be in progress is stopped immediately when XORH goes high. Place the jumpers JP2 in A and B positions to turn on the pass through mode.+  - If the master wants to communicate with the slave using the general call address, it can temporarily disable address translation by pulling XORH high. This disables address translation and keeps N1 and N2 on regardless of the activity on the buses, turning on the Pass Through Mode (N1 connects SCLIN to SCLOUT while N2 connects SDAIN to SDAOUT).  Any translation that may be in progress is stopped immediately when XORH goes high. Place the jumpers JP2 in A and B positions to turn on the Pass Through Mode.
  
  
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   - Connect the P1 connector of the second [[adi>en/products/adt7420.html |EVAL-ADT7420-PMDZ]] temperature sensor boards to the P7 pmod connector on the EVAL-LTC4317-PMDZ board.   - Connect the P1 connector of the second [[adi>en/products/adt7420.html |EVAL-ADT7420-PMDZ]] temperature sensor boards to the P7 pmod connector on the EVAL-LTC4317-PMDZ board.
   - Repeat the steps above with place the jumper on JP1 in B position only on EVAL-LTC4317-PMDZ. This will power up Bus 2 on the downstream which will allow the [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADICUP3029.html|EVAL-ADICUP3029]] to communicate with the second temperature sensor board on the downstream without needing Address Translation.   - Repeat the steps above with place the jumper on JP1 in B position only on EVAL-LTC4317-PMDZ. This will power up Bus 2 on the downstream which will allow the [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADICUP3029.html|EVAL-ADICUP3029]] to communicate with the second temperature sensor board on the downstream without needing Address Translation.
-  - The Figures below shows how the hardware should be set-up:+  - The hardware should be set-up as shown below:
 {{ :resources:eval:user-guides:interface-isolation:eval-ltc4317-pmdz:setup1.png?direct |}} {{ :resources:eval:user-guides:interface-isolation:eval-ltc4317-pmdz:setup1.png?direct |}}
  
resources/eval/user-guides/interface-isolation/eval-ltc4317-pmdz.txt · Last modified: 26 Jan 2022 18:56 by Naveen Afzal