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resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware [23 Feb 2018 23:19] – fixed typos Jeff Watson | resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware [01 Mar 2018 03:41] (current) – edited figures Jeff Watson | ||
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The project controls the activity of the EV-HT-200CDAQ1, | The project controls the activity of the EV-HT-200CDAQ1, | ||
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+ | ==== Source and Header File Organization ==== | ||
+ | The project is organized into .c and .h files. | ||
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+ | {{: | ||
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<WRAP center round box 100%> | <WRAP center round box 100%> | ||
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EV-HT-200CDAQ1 Firmware Flowchart | EV-HT-200CDAQ1 Firmware Flowchart | ||
</ | </ | ||
\\ | \\ | ||
<WRAP center round box 100%> | <WRAP center round box 100%> | ||
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Parser Routine Flow | Parser Routine Flow | ||
</ | </ | ||
- | ==== Source and Header File Organization ==== | ||
- | The project is organized into .c and .h files. | ||
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- | {{: | ||
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This section has tables showing the pins, peripherals and interrupts used in the project. | This section has tables showing the pins, peripherals and interrupts used in the project. | ||
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==== MCU Pin Use Table ==== | ==== MCU Pin Use Table ==== | ||
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The ADC servicing is done in the timer interrupt service routine. | The ADC servicing is done in the timer interrupt service routine. | ||
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Data collected from the ADC is stored in a dedicated 16kbyte (16,384) buffer that will later be sent out a UART port to a PC host. The buffer can be divided into segments for different ADC channels as set by the incoming command. | Data collected from the ADC is stored in a dedicated 16kbyte (16,384) buffer that will later be sent out a UART port to a PC host. The buffer can be divided into segments for different ADC channels as set by the incoming command. | ||
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The SPI clock is set to 25 MHz. This is half the MCU system clock and the fastest achievable SPI master clock from the VA10800. | The SPI clock is set to 25 MHz. This is half the MCU system clock and the fastest achievable SPI master clock from the VA10800. | ||
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==== Aligning CNV signals for ADC0 & ADC1 ==== | ==== Aligning CNV signals for ADC0 & ADC1 ==== | ||
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One of the sampling timing requirements is that the CNV signals for ADC0 and ADC1 being exactly aligned. | One of the sampling timing requirements is that the CNV signals for ADC0 and ADC1 being exactly aligned. | ||
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==== External Trigger Mode ==== | ==== External Trigger Mode ==== | ||
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The below diagram shows the priority hierarchy. | The below diagram shows the priority hierarchy. | ||
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Due to some inherent interrupt blocking of FreeRTOS during task changes, a conflict can arise when the ADCs are being converted very rapidly, under 4us. During an acquisition experiment with sampling rate under 4us, the RTOS is temporarily disabled. | Due to some inherent interrupt blocking of FreeRTOS during task changes, a conflict can arise when the ADCs are being converted very rapidly, under 4us. During an acquisition experiment with sampling rate under 4us, the RTOS is temporarily disabled. | ||
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==== Temperature and Vcc Calculation ==== | ==== Temperature and Vcc Calculation ==== | ||
- | The RTD data sheet contains a table with resistance values for every 1C. Firmware has created a linear interpolation conversion program for 5 different regions in the -55C | + | The RTD data sheet contains a table with resistance values for every 1°C. Firmware has created a linear interpolation conversion program for 5 different regions in the -55°C to 200°C |
Both the RTD and VCC calculations account for a voltage divider network. | Both the RTD and VCC calculations account for a voltage divider network. | ||
- | <note important> | + | <note important> |
===== Performance ===== | ===== Performance ===== | ||
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As shown in the below diagram, the fastest ADC sample rate using interrupt is 413 kHz which corresponds to 2.4ųs. | As shown in the below diagram, the fastest ADC sample rate using interrupt is 413 kHz which corresponds to 2.4ųs. | ||
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==== UART RX Performance ==== | ==== UART RX Performance ==== | ||
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The RTOS scheduler is allocating 50% of the CPU bandwidth for handling the acquisition task. Some activities are interrupt driven and the actual CPU cycles spent on these are dependent on sampling rate and amount of data being transmitted to a PC. The following table can be used to estimate the available CPU bandwidth. | The RTOS scheduler is allocating 50% of the CPU bandwidth for handling the acquisition task. Some activities are interrupt driven and the actual CPU cycles spent on these are dependent on sampling rate and amount of data being transmitted to a PC. The following table can be used to estimate the available CPU bandwidth. | ||
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===== Compiler and IDE ===== | ===== Compiler and IDE ===== |