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resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware [21 Feb 2018 03:13] – draft3 Jeff Watsonresources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware [01 Mar 2018 03:41] (current) – edited figures Jeff Watson
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 The project controls the activity of the EV-HT-200CDAQ1, which has three Analog Devices ADCs, an analog multiplexer and conditioning circuitry.  Users can send commands to the board via a PC (COM port over USB).  The board will respond by either executing the command or issuing an error message.  Responses to commands are transmitted on the UART back to the PC. The project controls the activity of the EV-HT-200CDAQ1, which has three Analog Devices ADCs, an analog multiplexer and conditioning circuitry.  Users can send commands to the board via a PC (COM port over USB).  The board will respond by either executing the command or issuing an error message.  Responses to commands are transmitted on the UART back to the PC.
 +
 +==== Source and Header File Organization ====
 +The project is organized into .c and .h files.  The following tables summarizes the contents of more salient files. 
 +
 +{{:resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_files.png?nolink&600|}}
 +
  
  
 ===== Firmware Function Overview ===== ===== Firmware Function Overview =====
  
-A simplified flow diagram is shown in below The ADC sampling engine is time critical and is explained in a later section.  +A simplified flow diagram is shown in below.   The ADC sampling engine is time critical and is explained in a later section.  
  
 <WRAP center round box 100%> <WRAP center round box 100%>
-{{:resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_flow.png?nolink|}}+{{:resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_flow.png?direct|}}
 EV-HT-200CDAQ1 Firmware Flowchart EV-HT-200CDAQ1 Firmware Flowchart
 </WRAP> </WRAP>
 \\ \\
 <WRAP center round box 100%> <WRAP center round box 100%>
-{{:resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_parser.png?nolink|}}+{{:resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_parser.png?direct|}}
 Parser Routine Flow Parser Routine Flow
 </WRAP> </WRAP>
  
-==== Source and Header File Organization ==== 
-The project is organized into .c and .h files.  The following tables summarizes the contents of more salient files.  
- 
-{{:resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_files.png?nolink|}} 
  
  
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 This section has tables showing the pins, peripherals and interrupts used in the project.  All other GPIO pins, timers and peripherals can be used by the end user’s application.  This section has tables showing the pins, peripherals and interrupts used in the project.  All other GPIO pins, timers and peripherals can be used by the end user’s application. 
  
-{{:resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_connections.png?nolink|}}+{{:resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_connections.png?direct|}}
  
 ==== MCU Pin Use Table ==== ==== MCU Pin Use Table ====
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 The ADC servicing is done in the timer interrupt service routine.  The conversion will begin on the rising edge of a timer output and the ISR is called on the falling edge as shown in diagram below.  The ADC servicing is done in the timer interrupt service routine.  The conversion will begin on the rising edge of a timer output and the ISR is called on the falling edge as shown in diagram below. 
  
-{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_adcreadseq.png?nolink |}}+{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_adcreadseq.png?direct |}}
  
 Data collected from the ADC is stored in a dedicated 16kbyte (16,384) buffer that will later be sent out a UART port to a PC host.  The buffer can be divided into segments for different ADC channels as set by the incoming command.  The 16kbyte buffer is storing 16-bit conversions, thus this is an 8Ksample buffer. Data collected from the ADC is stored in a dedicated 16kbyte (16,384) buffer that will later be sent out a UART port to a PC host.  The buffer can be divided into segments for different ADC channels as set by the incoming command.  The 16kbyte buffer is storing 16-bit conversions, thus this is an 8Ksample buffer.
  
-<note important>To achieve the fastest sampling rate, software was written in a non-conventional way and the compiler optimization must be set to level 3 for maximum performance.  Some compilers automatically store all registers before starting an ISR.  This is not allowed if 2.4us conversion rates are expected. +<note important>To achieve the fastest sampling rate, software was written in a non-conventional way and the compiler optimization must be set to level 3 for maximum performance.  Some compilers automatically store all registers before starting an ISR.  This is not allowed if 2.4ųs conversion rates are expected. 
 </note> </note>
  
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 The SPI clock is set to 25 MHz.  This is half the MCU system clock and the fastest achievable SPI master clock from the VA10800.  Special settings are required to make this operate correctly at this speed.  The data in (MISO) of the MCU must be setup to capture the ADC’s output on the falling edge of the SPI SCK signal.  The filtering for these pins must be disabled and the synchronous setting disabled.  FILTER = 0x1.   The SPI clock is set to 25 MHz.  This is half the MCU system clock and the fastest achievable SPI master clock from the VA10800.  Special settings are required to make this operate correctly at this speed.  The data in (MISO) of the MCU must be setup to capture the ADC’s output on the falling edge of the SPI SCK signal.  The filtering for these pins must be disabled and the synchronous setting disabled.  FILTER = 0x1.  
  
-{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_spi_explanation.png?nolink |}}+{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_spi_explanation.png?direct |}}
  
 ==== Aligning CNV signals for ADC0 & ADC1 ==== ==== Aligning CNV signals for ADC0 & ADC1 ====
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 One of the sampling timing requirements is that the CNV signals for ADC0 and ADC1 being exactly aligned.  This is accomplished by using the cascade function of the Vorago timers.  One timer, TIM_0, is used to trigger two other timers that create the CNV signals using the PWM function.   One of the sampling timing requirements is that the CNV signals for ADC0 and ADC1 being exactly aligned.  This is accomplished by using the cascade function of the Vorago timers.  One timer, TIM_0, is used to trigger two other timers that create the CNV signals using the PWM function.  
  
-{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_timer_cascade.png?nolink |}}+{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_timer_cascade.png?direct|}}
  
 ==== External Trigger Mode ==== ==== External Trigger Mode ====
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 ==== VCC and RTD Sampling with Burst ==== ==== VCC and RTD Sampling with Burst ====
  
-The viewer program on the PC expects VCC and RTD information to go along with every burst sequence.  Four samples of channel 8 (VCC) and channel 9 (RTD) are conducted at the end of each burst sequence.  An average is calculated and reported as the first line of each Burst experiment UART output sequence. The sample rate for these conversions is set to 10 second independent of what the $setacq calls out.  This was done to ensure the analog multiplexer and associated op-amp have time to stabilize.+The viewer program on the PC expects VCC and RTD information to go along with every burst sequence.  Four samples of channel 8 (VCC) and channel 9 (RTD) are conducted at the end of each burst sequence.  An average is calculated and reported as the first line of each Burst experiment UART output sequence. The sample rate for these conversions is set to 10ųs independent of what the $setacq calls out.  This was done to ensure the analog multiplexer and associated op-amp have time to stabilize.
  
 ===== UART output (“output.c” & “uart.c”) ===== ===== UART output (“output.c” & “uart.c”) =====
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 The below diagram shows the priority hierarchy.  The OS will jump between the data acquisition task and the User task.  Interrupts are implemented for the ADC sampling, the tick timer and the UART receive process.  Either the data acquisition task or the user task can be interrupted when one of these events occurs. The below diagram shows the priority hierarchy.  The OS will jump between the data acquisition task and the User task.  Interrupts are implemented for the ADC sampling, the tick timer and the UART receive process.  Either the data acquisition task or the user task can be interrupted when one of these events occurs.
  
-{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_taskdiagram.png?nolink |}}+{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_taskdiagram.png?direct |}}
  
 Due to some inherent interrupt blocking of FreeRTOS during task changes, a conflict can arise when the ADCs are being converted very rapidly, under 4us.  During an acquisition experiment with sampling rate under 4us, the RTOS is temporarily disabled.   Due to some inherent interrupt blocking of FreeRTOS during task changes, a conflict can arise when the ADCs are being converted very rapidly, under 4us.  During an acquisition experiment with sampling rate under 4us, the RTOS is temporarily disabled.  
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 ==== Temperature and Vcc Calculation ==== ==== Temperature and Vcc Calculation ====
  
-The RTD data sheet contains a table with resistance values for every 1C.  Firmware has created a linear interpolation conversion program for 5 different regions in the -55C to 200C range.  +The RTD data sheet contains a table with resistance values for every 1°C.  Firmware has created a linear interpolation conversion program for 5 different regions in the -55°C to 200°C range.  
  
 Both the RTD and VCC calculations account for a voltage divider network.   Both the RTD and VCC calculations account for a voltage divider network.  
-<note important>RTD and VCC calculations were modified to account for two 100k resistors used to bias the output of the Analog Multiplexor.  See the schematic for details on this.</note>  +<note important>RTD and VCC calculations were modified to account for two 100kΩ resistors used to bias the output of the Analog Multiplexor.  See the schematic for details on this.</note>  
  
 ===== Performance ===== ===== Performance =====
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 ==== ADC Sample Rate ==== ==== ADC Sample Rate ====
  
-As shown in the below diagram, the fastest ADC sample rate using interrupt is 413 kHz which corresponds to 2.4us.+As shown in the below diagram, the fastest ADC sample rate using interrupt is 413 kHz which corresponds to 2.4ųs.
  
-{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_burstmode1.png?nolink&|}}+{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_burstmode1.png?direct&|}}
  
-{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_burstmode2.png?nolink |}}+{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_burstmode2.png?direct |}}
  
 ==== UART RX Performance ==== ==== UART RX Performance ====
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 The RTOS scheduler is allocating 50% of the CPU bandwidth for handling the acquisition task.  Some activities are interrupt driven and the actual CPU cycles spent on these are dependent on sampling rate and amount of data being transmitted to a PC.  The following table can be used to estimate the available CPU bandwidth.  The RTOS scheduler is allocating 50% of the CPU bandwidth for handling the acquisition task.  Some activities are interrupt driven and the actual CPU cycles spent on these are dependent on sampling rate and amount of data being transmitted to a PC.  The following table can be used to estimate the available CPU bandwidth. 
  
-{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_cpubandwidth.png?nolink |}}+{{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware_cpubandwidth.png?nolink&600 | }}
  
 ===== Compiler and IDE ===== ===== Compiler and IDE =====
resources/eval/user-guides/high-temp/ev-ht-200cdaq1/firmware.1519179189.txt.gz · Last modified: 21 Feb 2018 03:13 by Jeff Watson

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