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resources:eval:user-guides:cn0561:hdl [25 Jul 2023 14:59] – old revision restored Michael Hennerichresources:eval:user-guides:cn0561:hdl [31 Jul 2023 07:41] (current) – Laurentiu Popa
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 More information about the framework can be found in the [[:resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] wiki page. The reference design uses the [[/resources/fpga/peripherals/spi_engine|SPI Engine Framework]] to interface with the AD4134 ADC.The design only supports the slave mode with both DCLK and ODR generated by the FPGA. The device sends data on the 4 DIN bits. More information about the framework can be found in the [[:resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] wiki page. The reference design uses the [[/resources/fpga/peripherals/spi_engine|SPI Engine Framework]] to interface with the AD4134 ADC.The design only supports the slave mode with both DCLK and ODR generated by the FPGA. The device sends data on the 4 DIN bits.
  
-{{:resources:fpga:docs:cn0561_hdl_2.svg|spi engine block diagram}}+{{:resources:fpga:docs:cn0561_hdl_6.svg|spi engine block diagram}}
  
 In order to build the HDL design the user has to go through the following steps: In order to build the HDL design the user has to go through the following steps:
resources/eval/user-guides/cn0561/hdl.txt · Last modified: 31 Jul 2023 07:41 by Laurentiu Popa

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