The HDL reference design for the CN0561 provides all the interfaces that are necessary to interact with the device using a Xilinx FPGA development board.
The design has all the necessary infrastructure to acquire data from the AD4134 24-bit 4-channel precision alias free ADC device, supporting continuous data capture at maximum 1.5 MSPS data rate however, due to a hardware limitation, the Cora-Z7s variant will only support a maximum data clock of 24MHz in contrast with 48MHz supported on the Zedboard.
The design targeted to the Zedboard, which is a low cost FPGA carrier board from Digilent, using a Zynq-7000 re-programmable SoC from Xilinx.
|P10||Mounted||MODE and DEC0/DCLKIO|
|P13||1-2||Current sources and fault protection powered from board ±15V sources|
|P15||1-2||Current sources and fault protection powered from board ±15V sources|
The design is built upon ADI's generic HDL reference design framework. More information about the framework can be found in the ADI Reference Designs HDL User Guide wiki page. The reference design uses the SPI Engine Framework to interface with the AD4134 ADC.The design only supports the slave mode with both DCLK and ODR generated by the FPGA. The device sends data on the 4 DIN bits.
In order to build the HDL design the user has to go through the following steps: