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Table of Contents
EVAL-CN0585-FMCZ User Guide
The EVAL-CN0585-FMCZ Low Latency Development Kit (LLDK) board is a development platform consisting of 4 x 16-bit ADC channels and 4 x 16-bit DAC channels that are interfaced with an FPGA through the FMC Low Pin Count (LPC) Connector.
The EVAL-CN0585-FMCZ board provides a complete data acquisition and signal generation platform with onboard power rails, voltage monitoring, logic level translation, general purpose I/O, I2C, SPI, and an AFE board connector.
The key performance benefit of the EVAL-CN0585-FMCZ system is the ability to perform a complete capture and conversion of precision analog input data in <70ns with the ADC module and generate a settled full-scale analog output in <250ns from initial data written to the DAC.
Connections and Configurations
Receive Channel
The EVAL-CN0585-FMCZ board has four ADAQ23876 16Bit 15MSPS Data Acquisition µModules to capture analog data from the AFE board connector. The Data Acquisition µModules are configured to simultaneously sample the four input channels. The data acquired by the ADAQ23876 is routed to the FPGA through the FMC LPC connector using a serial low voltage differential signaling (LVDS) digital interface in a two-lane output mode. The ADAQ23876 has pin configurable input voltage span with configurable gain/attenuation options: 0.37, 0.73, 0.87, 1.38, and 2.25, providing input voltage span ranges of ±10 V, ±5 V, ±4.096 V, ±2.5 V, and ±1.5 V. The gain/attenuation functions are accessible through the AFE board connector pins. As an example the EVAL-CN0584-EBZ is available for HIL applications.
Transmit Channel
The EVAL-CN0585-FMCZ board has two AD3552R 16-bit 33MUPS DACs that provide four analog output signals to the AFE board connector. Data is transferred to the AD3552R DAC from the FPGA through the FMC LPC connector using a Quad-SPI dual data rate interface.
The AD3552R has a pin-configurable output voltage span that can be configured through the AFE board connector. Multiple output span ranges can be configured, such as 0 V to 5 V, −5 V to +5 V, −10 V to +10 V, and custom intermediate ranges with full 16-bit resolution.
Voltage Reference
The default ADC configuration uses an internal 2.048V 5ppm/°C voltage reference with an optional external LTC6655 2.048V 5ppm/°C reference that is jumper selectable.
The default DAC configuration uses an internal 2.5V 3ppm/°C voltage reference with an optional external ADR4525 2.5V 2ppm/°C reference that is jumper selectable.
| VREF | Jumper Settings |
|---|---|
| ADC_VREF | Short P5 |
| DAC_VREF | Short P4 |
Voltage Monitoring
The EVAL-CN0585-FMCZ board provides voltage monitoring capability for the power supply rails. The circuit consists of an AD7291 8-Channel, I2C, 12-Bit SAR ADC, and resistive dividers to each power rail. The negative power supply rails are biased positive with a buffered 2.5V reference supplied by the AD7291.
The default I2C address of the AD7291 is 0x20. Resistors R13, R14, R17, and R18 can be used to select alternate addressing.
Logic Level Translators
Several logic-level translators are used on the board to interface with the FMC connector signals and the various logic levels used on the board. The FMC connector signal levels are driven by the VIO voltage supplied from the FPGA board.
GPIO
A GPIO interface is provided by a MAX7301ATL+ I/O Expander connected to the SPI interface on the SPIO_CSB0 chip select interface. The GPIO outputs are controlled by writing to the MAX7301ATL+ via the SPI interface provided on the FMC connector. Four GPIO signals are utilized on the EVAL-CN0585-FMCZ board to control the power-down interface of the ADAQ23875 Data Acquisition µModules. Eight GPIO signals are level-shifted and provided to the AFE board connector for control signals on the AFE board.
I2C
The I2C interface is provided from the FPGA FMC connector and is made available to the EVAL-CN0585-FMCZ board and the user via the AFE board connector. On the EVAL-CN0585-FMCZ board the I2C interface is used to communicate with an EEPROM that is required by the Vita 57.1 Standard for board identification and IO characteristics, and the AD7291 voltage monitoring ADC.
SPI
The EVAL-CN0585-FMCZ board provides a “classic” SPI interface for the user on SPI0 from the FMC connector. Communication with the MAX7301ATL+ GPIO expander is enabled by chip select SPIO_CSB0. SPI_CSB1 originated from the FMC interface and is connected to the AFE board connector so that the user can attach a custom secondary SPI device to the AFE board. The second SPI0_CSB1 is not initialized in the Linux device tree, as the initialization requires as well information such as SPI transmission mode, phase, and polarity. Two Quad-SPI interfaces (DAC0/1 and DAC2/3) are provided by the FMC interface to handle communications and data transfer to the four AD3552R DAC channels.
Application-specific Analog Front-End Connector
The AFE connector interface provides six signal connections for each of the four ADAQ23876 Data Acquisition µModules. The six signal connections allow the user to set the input voltage range of the differential amplifier input. Configuration resistors, if used, should be placed as close as possible to the AFE board connector. Please refer to the ADQ23876 Datasheet for more configuration details.
| Input Range | Input Signal on Pins | Feedback Connections |
|---|---|---|
| +/- 10V (Default) | ADCx_IN2P, ADCx_IN2N | ADCx_OUTP and ADCx_IN1N pins Shorted ADCx_OUTN and ADCx_IN1P pins Shorted |
| +/- 5V | ADCx_IN1P, ADCx_IN1N | ADCx_OUTP and ADCx_IN2N pins Shorted ADCx_OUTN and ADCx_IN2P pins Shorted |
| +/- 4.096V | ADCx_IN2P, ADCx_IN2N | No Connect |
| +/- 2.5V | ADCx_IN1P, ADCx_IN1N | No Connect |
| +/- 1.5V | ADCx_IN1P/ADCx_IN2P Shorted ADCx_IN1N/ADCx_IN2N Shorted | No Connect |
The AFE connector interface provides three signal connections for each of the four DAC output channels. The three signal connections allow the user to set the output voltage range of the AD3552R DAC. Configuration resistors, if used, should be placed as close as possible to the AFE board connector. The AD3552R uses a current steering DAC architecture with a VREF voltage of 2.5 V. The DAC current is converted to a voltage using an external TIA. The DAC outputs are observed on signals DAC0, DAC1, DAC2, and DAC3. The DACx outputs are fed back into the AD3552R gain configuration pins for each DAC channel. The table below details the configuration connections for each of the output voltage ranges of each of the DAC output channels.
| Channel | Output Span | VZS (V) | VFS (V) | Feedback Connection |
|---|---|---|---|---|
| CH0 | +/- 10V (Default) | -10.382 | 10.380 | DAC0 to DAC0_RFB0 |
| +/- 5V | -5.165 | 5.166 | DAC0 to DAC0_RFB0_X2 | |
| 10V | -0.165 | 10.163 | DAC0 to DAC0_RFB0_X2 | |
| 5V | -0.078 | 5.077 | DAC0 to DAC0_RFB0_X1 | |
| 2.5V | -0.198 | 2.701 | DAC0 to DAC0_RFB0_X1 | |
| CH1 | +/- 10V (Default) | -10.382 | 10.380 | DAC1 to DAC1_RFB1 |
| +/- 5V | -5.165 | 5.166 | DAC1 to DAC1_RFB1_X2 | |
| 10V | -0.165 | 10.163 | DAC1 to DAC1_RFB0_X2 | |
| 5V | -0.078 | 5.077 | DAC1 to DAC1_RFB1_X1 | |
| 2.5V | -0.198 | 2.701 | DAC1 to DAC1_RFB1_X1 | |
| CH2 | +/- 10V (Default) | -10.382 | 10.380 | DAC2 to DAC2_RFB0 |
| +/- 5V | -5.165 | 5.166 | DAC2 to DAC2_RFB0_X2 | |
| 10V | -0.165 | 10.163 | DAC2 to DAC2_RFB0_X2 | |
| 5V | -0.078 | 5.077 | DAC2 to DAC2_RFB0_X1 | |
| 2.5V | -0.198 | 2.701 | DAC2 to DAC2_RFB0_X1 | |
| CH3 | +/- 10V (Default) | -10.382 | 10.380 | DAC3 to DAC3_RFB1 |
| +/- 5V | -5.165 | 5.166 | DAC3to DAC3_RFB1_X2 | |
| 10V | -0.165 | 10.163 | DAC3to DAC3_RFB1_X2 | |
| 5V | -0.078 | 5.077 | DAC3 to DAC3_RFB1_X1 | |
| 2.5V | -0.198 | 2.701 | DAC3 to DAC3_RFB1_X1 |
Please refer to the AD3552R Datasheet for more configuration details.
The AFE board connector provides an input/output interface to the EVAL-CN0585-FMCZ board. The interface provides connections to the analog IO, ADC/DAC gain settings, GPIO, I2C, SPI, aux power, and four direct FMC connections to allow system flexibility interfacing with custom Analog Front End (AFE) designs that are provided by ADI or can be custom designed by the user.
The AFE board connector on the EVAL-CN0585-FMCZ board is a Samtec High-Density socket connector.
Connector Pinout (Rev B)
LED Indicators
Once the board is connected to the host, and power is delivered, the green LED DS1 should be turned on.
Power Supply Considerations and Configuration
The Rev. B of the EVAL-CN0585-FMCZ board is powered through the USB-C connector of the board.
The board can also be powered from the FMC connector by adding resistor R9 and removing resistor R10, but it is not recommended as the current consumption exceeds the FMC standard current limit.
System Setup Using a Zed Board
The EVAL-CN0585-FMCZ is fully supported using a Zedboard.
Demo Requirements
The following is a list of items needed to replicate this demo.
- Hardware
- ZedBoard Rev D or later board
- 12Vdc, 3A power supply
- 16GB (or larger) Class 10 (or faster) micro-SD card (included in the box)
- USB-C power source (included in the box)
- Micro-USB cable
- Ethernet cable
- User interface setup (choose one):
- HDMI monitor, keyboard, and mouse plugged directly into the Zedboard
- Host Windows/Linux/Mac computer on the same network as the Zedboard
- Software
- You need a Host PC (Windows or Linux)
- A UART terminal (Putty/Tera Term/Minicom, etc.), Baud rate 115200 (8N1)
- IIO Scope Download
Loading Image on SD Card
The box includes a pre-programmed SD card. You can skip this and go to the Setting up the Hardware section if using this card.
To boot the Zedboard and control the EVAL-CN0585-FMCZ, you will need to install ADI Kuiper Linux on an SD card. Complete instructions, including where to download the SD card image, how to write it to the SD card, and how to configure the system are provided on the Kuiper Linux page.
Configuring the SD Card
Follow the configuration procedure under Configuring the SD Card for FPGA Projects on the Kuiper Linux page. Copy the following files onto the boot directory to configure the SD card:
- uImage file for Zynq
- BOOT.BIN specific to your EVAL-CN0585-FMCZ + ZedBoard
- devicetree.dtb for Zynq specific to your EVAL-CN0585-FMCZ + ZedBoard
Setting up the Hardware
You will need to:
- Insert the SD-CARD into the SD Card Interface Connector (J12).
- Connect the EVAL-CN0585-FMCZ board into the ZedBoard FMC connector.
- Connect USB UART J14 (Micro USB) to your host PC.
- Plug your ethernet cable into the RJ45 ethernet connector(J11).
- Plug the Power Supply into the 12V Power input connector (J20) (DO NOT turn the device on).
- Set the jumpers as seen in the below picture:
- Loopback the DAC's output channels to the ADC's inputs as seen in the below picture:
- Turn it on.
- Wait ~30 seconds for the “DONE” LED to turn blue. This is near the DISP1.
All the products described on this page include ESD (electrostatic discharge) sensitive devices. Electrostatic charges as high as 4000V readily accumulate on the human body or test equipment and can discharge without detection.
Although the boards feature ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. This includes removing static charge on external equipment, cables, or antennas before connecting to the device.
Application Software (both locally and remotely on the FPGA)
Hardware Connection
The Libiio is a library used for interfacing with IIO devices and is required to be installed on your computer.
Download and Install the latest Libiio package on your machine.
To be able to connect your device, the software must be able to create a context. The context creation in the software depends on the backend used to connect to the device as well as the platform where the EVAL-CN0585-FMCZ is attached. The Zedboard running ADI Kuiper Linux is currently the only platform supported for the CN0585. The user needs to supply a URI which will be used in the context creation.
The iio_info command is a part of the libIIO package that reports all IIO attributes.
Upon installation, simply enter the command on the terminal command line to access it.
For FPGA(Zedboard) Direct Local Access:
iio_info
For Windows machine connected to an FPGA(Zedboard):
iio_info -u ip:<ip address of your ip>
Example:
- If your Zedboard has the IP address 169.254.92.202, you have to use iio_info -u ip::169.254.92.202 as your URI
Do note that the Windows machine and the FPGA board should be connected to the same network for the machine to detect the device.
IIO Oscilloscope
Make sure to download/update to the latest version of IIO-Oscilloscope found on this linkhttps://github.com/analogdevicesinc/iio-oscilloscope/releases
- Once done with the installation or an update of the latest IIO-Oscilloscope, open the application. The user needs to supply a URI which will be used in the context creation of the IIO Oscilloscope and the instructions can be seen in the previous section.
- Press refresh to display available IIO Devices and press connect.
- After the board is connected set the raw value to 1 for the following output voltages of the one-bit-adc-dac device which is the controller for the MAX7301ATL+ I/O Expander. This step will configure the value for the following pins which are connected to the MAX7301ATL+ I/O Expander:
| one-bit-adc-dac device channel | Schematic PIN |
|---|---|
| Voltage0 | GPIO0_VIO |
| Voltage1 | GPIO1_VIO |
| Voltage2 | GPIO2_VIO |
| Voltage3 | GPIO3_VIO |
| Voltage4 | GPIO6_VIO |
| Voltage5 | GPIO7_VIO |
| Voltage6 | PAD_ADC0 |
| Voltage7 | PAD_ADC1 |
| Voltage8 | PAD_ADC2 |
| Voltage9 | PAD_ADC3 |
- Select the desired input source for both AD3552R devices.
Even if the input source is set to adc_input or ramp_input the steps regarding the DAC Data Management tab have to be followed.
- Select the desired output range for both AD3552R devices.
Make sure you don't try to read/write the output_range attribute when the stream_status is in start_stream or start_stream_synced.
- From the DAC Data Manager Window select the output channels of the DAC and enable the cyclic buffer.
- Load an example file from the IIO Oscilloscope/lib/osc/waveforms folder.
If the source is set as dma_input and the data from all 4 channels needs to be synchronized make sure that you press the load button for the axi-ad3552r-1 device first then for axi-ad3552r-0.
- Click on the load button.
If the source is set as dma_input and the data from all 4 channels needs to be synchronized make sure that you write the start_stream_synced for the axi-ad3552r-1 device first then for axi-ad3552r-0.
- Select the stream_status IIO Attribute and start the stream (start_stream_synced means that all 4 channels are updated at the same time and the data streaming process waits for both DACs to be started).
If the source is set as dma_input and the data from all 4 channels needs to be synchronized make sure that you write the start_stream_synced for the
axi-ad3552r-1 device first then for axi-ad3552r-0.
- After the stream_status has been written you should see the data capture window:
Note that there is a phase delay between voltage0/voltage2 and voltage1/voltage3 because the DAC device channels are updated consecutively See the DAC UPDATE MODES section in AD3552R Data Sheet.
If you intend to stop the stream transmission and start it again synchronized set the stream_status IIO Attribute to stop_stream for axi-ad3552r-1 device first then for the axi-ad3552r-0 device.
PyADI-IIO
PyADI-IIO is a Python abstraction module for ADI hardware with IIO drivers to make them easier to use. This module provides device-specific APIs built on top of the current libIIO Python bindings. These interfaces try to match the driver naming as much as possible without the need to understand the complexities of libIIO and IIO.
Follow the step-by-step procedure on how to install, configure, and set up PYADI-IIO and install the necessary packages/modules needed by referring to this link.
Running the example
Github link for the Python sample script: CN0585 Python Example
After installing and configuring PYADI-IIO on your machine, you are now ready to run Python script examples. In our case, run the cn0585_fmcz_example.py found in the examples folder.
D:\pyadi-iio>export PYTHONPATH=D:/pyadi-iio/ D:\pyadi-iio>python examples/cn0585_fmcz_example.py ip:your_board_ip
Press enter and you will get these readings:
$ python examples/cn0585_fmcz_example.py uri: ip:your_board_ip ############# EEPROM INFORMATION ############ read 256 bytes from /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-1/1-0050/eeprom Date of Man : Fri Jan 20 08:11:00 2023 Manufacturer : Analog Devices Product Name : LLDK-LTC2387-AD3552R Serial Number : 56864654 Part Number : 1234 FRU File ID : 12131321 PCB Rev : VB PCB ID : HIL BOM Rev : VC Uses LVDS : Y ############################################# GPIO4_VIO state is: 0 GPIO5_VIO state is: 0 Voltage monitor values: Channel : temp0 : 49.25 Deg. C Channel : voltage0 : 2.26745605283 V Channel : voltage1 : 0.6274414057359999 V Channel : voltage2 : 2.061157224874 V Channel : voltage3 : 0.7531738275079999 V Channel : voltage4 : 2.092285154536 V Channel : voltage5 : 2.084960935792 V Channel : voltage6 : 2.2534179669039998 V Channel : voltage7 : 1.80969238133 V AXI4-Lite 0x108 register value: 0x2 AXI4-Lite 0x10c register value: 0xB Sample data min: 0 Sample data max: 65535 input_source:dac0: adc_input input_source:dac1: adc_input Maximum measured voltage 0 : 10.115187500000001 Maximum measured voltage 1 : 0.00103125 Maximum measured voltage 2 : 0.00034375000000000003 Maximum measured voltage 3 : 0.00103125 Minimum measured voltage 0: 10.107625 Minimum measured voltage 1: -0.00034375000000000003 Minimum measured voltage 2: -0.00103125 Minimum measured voltage 3: -0.00034375000000000003
The following window will pop up:
If you plan to transmit multiple cycles of synchronous stream, make sure axi-ad3552r-1 is started/stopped first, then axi-ad3552r-0.
MATLAB and Simulink
Required MATLAB Add-Ons:
Github link for the Matlab sample script: CN0585StreamingTest.m
The steps described in the Analog Devices Transceiver Toolbox For MATLAB and Simulink page have to be followed to configure the Matlab/Simulink project using the MathWorks HDL Workflow Advisor.
Device Control and Data Streaming
Remote data streaming to and from hardware is made available through system object interfaces, which are unique for each component or platform. The hardware interfacing system objects provide a since class to both configure a given platform and move data back and forth from the device. After running the CN0585StreamingTest.m example The following window will pop up:
This is the terminal output that can be observed if the HDL Targeting with HDL-Coder flow was followed and there are 2 AXI4-Lite registers in the HDL DUT IP:
If you plan to transmit multiple cycles of synchronous stream, make sure axi-ad3552r-1 is started/stopped first, then axi-ad3552r-0.
HDL Targeting with HDL-Coder
Precision Toolbox supports the IP Core generation flow from MathWorks which allows for automated integration of DSP into HDL reference designs from Analog Devices. This workflow will take Simulink subsystems, run HDL-Coder to generate source Verilog, and then integrate that into a larger reference design.
Transmit reference design (Tx)
| Interface signal name | Width | Description |
|---|---|---|
| CN0585 ADC Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. |
| CN0585 ADC Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. |
| CN0585 ADC Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. |
| CN0585 ADC Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. |
| IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. |
| CN0585 DAC Data 0 OUT | 16 | AD3552R_0 DAC 0 channel data. To be used as input into the AD3552R interface IP. |
| CN0585 DAC Data 1 OUT | 16 | AD3552R_0 DAC 1 channel data. To be used as input into the AD3552R interface IP. |
| CN0585 DAC Data 2 OUT | 16 | AD3552R_1 DAC 0 channel data. To be used as input into the AD3552R interface IP. |
| CN0585 DAC Data 3 OUT | 16 | AD3552R_1 DAC 1 channel data. To be used as input into the AD3552R interface IP. |
| IP Data Valid OUT | 1 | Output signal that has to be logic '1' for a clock cycle period when the data starts to be valid. |
| IP Load Tx Data OUT | 1 | Custom IP output signal used to notify the design that the IP is ready to receive new input data. The duration must be 1 clock cycle. |
HDL Block diagram for Tx Reference design
Recieve reference design (Rx)
| Interface signal name | Width | Description |
|---|---|---|
| IP Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. |
| IP Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. |
| IP Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. |
| IP Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. |
| IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. |
| IP Data 0 OUT | 16 | ADAQ23876 ADC 0 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 1 OUT | 16 | ADAQ23876 ADC 1 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 2 OUT | 16 | ADAQ23876 ADC 2 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 3 OUT | 16 | ADAQ23876 ADC 3 channel data. To be used as input for the ADC CPAK IP. |
| IP Data Valid OUT | 1 | Output signal that has to be logic '1' for a clock cycle period when the data starts to be valid. |
HDL Block diagram for Rx Reference design
Transmit and Recieve reference design (Tx & Rx)
| Interface signal name | Width | Description |
|---|---|---|
| IP Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. |
| IP Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. |
| IP Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. |
| IP Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. |
| CN0585 ADC Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. |
| CN0585 ADC Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. |
| CN0585 ADC Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. |
| CN0585 ADC Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. |
| IP Valid Rx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. |
| IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. |
| IP Data 0 OUT | 16 | ADAQ23876 ADC 0 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 1 OUT | 16 | ADAQ23876 ADC 1 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 2 OUT | 16 | ADAQ23876 ADC 2 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 3 OUT | 16 | ADAQ23876 ADC 3 channel data. To be used as input for the ADC CPAK IP. |
| CN0585 DAC Data 0 OUT | 16 | AD3552R_0 DAC 0 channel data. To be used as input into the AD3552R interface IP. |
| CN0585 DAC Data 1 OUT | 16 | AD3552R_0 DAC 1 channel data. To be used as input into the AD3552R interface IP. |
| CN0585 DAC Data 2 OUT | 16 | AD3552R_1 DAC 0 channel data. To be used as input into the AD3552R interface IP. |
| CN0585 DAC Data 3 OUT | 16 | AD3552R_1 DAC 1 channel data. To be used as input into the AD3552R interface IP. |
| IP Data Valid OUT | 1 | Output signal that has to be logic '1' for a clock cycle period when the data starts to be valid. |
| IP Load Tx Data OUT | 1 | Custom IP output signal used to notify the design that the IP is ready to receive new input data. The duration must be 1 clock cycle. |
HDL Block diagram for Tx and Rx Reference design
Schematic, PCB Layout, Bill of Materials
EVAL-CN0585-FMCZ Design & Integration Files
- Schematics
- PCB Layout
- Bill of Materials
- Allegro Project
Additional Information and Useful Links
Reference Demos & Software
Hardware Registration
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resources/eval/user-guides/circuits-from-the-lab/cn0585.1684407188.txt.gz · Last modified: 18 May 2023 12:53 by Paul Pop