The most recent version of this page is a draft.
This version is outdated by a newer approved version.This version (29 May 2023 10:44) was approved by Paul Pop.The Previously approved version (29 May 2023 08:17) is available.
This version is outdated by a newer approved version.This version (29 May 2023 10:44) was approved by Paul Pop.The Previously approved version (29 May 2023 08:17) is available.This is an old revision of the document!
Table of Contents
EVAL-CN0584-EBZ User Guide
The EVAL-CN0584-EBZ Low Latency Development Kit (LLDK) board is a development platform consisting of 4 x 16-bit ADC channels and 4 x 16-bit DAC channels that are interfaced with an FPGA through the FMC Low Pin Count (LPC) Connector.
The LLDK board provides a complete data acquisition and signal generation platform with on-board power rails, voltage monitoring, logic level translation, general purpose I/O, I2C, SPI, and a personality interface connector.
The key performance benefit of the LLDK system is the ability to perform a complete capture and conversion of precision analog input data in <70ns with the ADC module and generate a settled full-scale analog output in <250ns from initial data written to the DAC.
Connections and Configurations
ADC Inputs
| Channel | Positive Input Signal | Negative Input Signal |
|---|---|---|
| Channel 0 | J1 | J2 |
| Channel 1 | J3 | J4 |
| Channel 2 | J5 | J6 |
| Channel 3 | J7 | J8 |
ADC Input Range Configuration
The CN0584 has configurable input voltage ranges of ±10 V(Default), ±5 V, ±4.096 V, ±2.5 V, and ±1.5 V. The input range can be changed by modifying resistor placements on the AFE Board.
| Channel | Input Voltage Range | AFE Board Modification |
|---|---|---|
| Channel 0 | ±10 V (default) | Include R19A, R21A, R22A, R24A; DNI R18A, R20A, R23A, R25A |
| ±5 V | Include R18A, R20A, R23A, R25A; DNI R19A, R21A, R22A, R24A | |
| ±4.096 V | Include R19A, R21A; DNI R18A, R20A, R22A, R23A, R24A, R25A | |
| ±2.5 V | Include R18A, R20A; DNI R19A, R21A, R22A, R23A, R24A, R25A | |
| ±1.5 V | Include R18A, R19A, R20A, R21A; DNI R22A, R23A, R24A, R25A | |
| Channel 1 | ±10 V (default) | Include R19B, R21B, R22B, R24B; DNI R18B, R20B, R23B, R25B |
| ±5 V | Include R18B, R20B, R23B, R25B; DNI R19B, R21B, R22B, R24B | |
| ±4.096 V | Include R19B, R21B; DNI R18B, R20B, R22B, R23B, R24B, R25B | |
| ±2.5 V | Include R18B, R20B; DNI R19B, R21B, R22B, R23B, R24B, R25B | |
| ±1.5 V | Include R18B, R19B, R20B, R21B; DNI R22B, R23B, R24B, R25B | |
| Channel 2 | ±10 V (default) | Include R19C, R21C, R22C, R24C; DNI R18C, R20C, R23C, R25C |
| ±5 V | Include R18C, R20C, R23C, R25C; DNI R19C, R21C, R22C, R24C | |
| ±4.096 V | Include R19C, R21C; DNI R18C, R20C, R22C, R23C, R24C, R25C | |
| ±2.5 V | Include R18C, R20C; DNI R19C, R21C, R22C, R23C, R24C, R25C | |
| ±1.5 V | Include R18C, R19C, R20C, R21C; DNI R22C, R23C, R24C, R25C | |
| Channel 3 | ±10 V (default) | Include R19D, R21D, R22D, R24D; DNI R18D, R20D, R23D, R25D |
| ±5 V | Include R18D, R20D, R23D, R25D; DNI R19D, R21D, R22D, R24D | |
| ±4.096 V | Include R19D, R21D; DNI R18D, R20D, R22D, R23D, R24D, R25D | |
| ±2.5 V | Include R18D, R20D; DNI R19D, R21D, R22D, R23D, R24D, R25D | |
| ±1.5 V | Include R18D, R19D, R20D, R21D; DNI R22D, R23D, R24D, R25D |
DAC Outputs
The CN0584 can support multiple output voltage ranges which can be configured, such as 0 V to 5 V, −5 V to +5 V, and −10 V to +10 V, and custom intermediate ranges with full 16-bit resolution. In order to change the output range, resistor placements on the AFE board must be modified and register settings must be applied.
| Channel | Output Span | VZS (V) | VFS (V) | AFE Board Modification | Register Setting |
|---|---|---|---|---|---|
| CH0 | +/- 10V (Default) | -10.382 | 10.380 | Include R9; DNI R10, R11 | CH0_CH1_OUTPUT_RANGE = 0x100 |
| +/- 5V | -5.165 | 5.166 | Include R10; DNI R9, R11 | CH0_CH1_OUTPUT_RANGE = 0x011 | |
| 10V | -0.165 | 10.163 | Include R10; DNI R9, R11 | CH0_CH1_OUTPUT_RANGE = 0x010 | |
| 5V | -0.078 | 5.077 | Include R11; DNI R9, R10 | CH0_CH1_OUTPUT_RANGE = 0x001 | |
| 2.5V | -0.198 | 2.701 | Include R11; DNI R9, R10 | CH0_CH1_OUTPUT_RANGE = 0x000 | |
| CH1 | +/- 10V (Default) | -10.382 | 10.380 | Include R12; DNI R13, R14 | CH0_CH1_OUTPUT_RANGE = 0x100 |
| +/- 5V | -5.165 | 5.166 | Include R13; DNI R12, R14 | CH0_CH1_OUTPUT_RANGE = 0x011 | |
| 10V | -0.165 | 10.163 | Include R13; DNI R12, R14 | CH0_CH1_OUTPUT_RANGE = 0x010 | |
| 5V | -0.078 | 5.077 | Include R14; DNI R12, R13 | CH0_CH1_OUTPUT_RANGE = 0x001 | |
| 2.5V | -0.198 | 2.701 | Include R14; DNI R12, R13 | CH0_CH1_OUTPUT_RANGE = 0x000 | |
| CH2 | +/- 10V (Default) | -10.382 | 10.380 | Include R15; DNI R16, R17 | CH2_CH3_OUTPUT_RANGE = 0x100 |
| +/- 5V | -5.165 | 5.166 | Include R16; DNI R15, R17 | CH2_CH3_OUTPUT_RANGE = 0x011 | |
| 10V | -0.165 | 10.163 | Include R16; DNI R15, R17 | CH2_CH3_OUTPUT_RANGE = 0x010 | |
| 5V | -0.078 | 5.077 | Include R17; DNI R15, R16 | CH2_CH3_OUTPUT_RANGE = 0x001 | |
| 2.5V | -0.198 | 2.701 | Include R17; DNI R15, R16 | CH2_CH3_OUTPUT_RANGE = 0x000 | |
| CH3 | +/- 10V (Default) | -10.382 | 10.380 | Include R18; DNI R19, R20 | CH2_CH3_OUTPUT_RANGE = 0x100 |
| +/- 5V | -5.165 | 5.166 | Include R19; DNI R18, R20 | CH2_CH3_OUTPUT_RANGE = 0x011 | |
| 10V | -0.165 | 10.163 | Include R19; DNI R18, R20 | CH2_CH3_OUTPUT_RANGE = 0x010 | |
| 5V | -0.078 | 5.077 | Include R20; DNI R18, R19 | CH2_CH3_OUTPUT_RANGE = 0x001 | |
| 2.5V | -0.198 | 2.701 | Include R20; DNI R18, R19 | CH2_CH3_OUTPUT_RANGE = 0x000 |
Voltage Reference
The default ADC configuration uses an internal 2.048V 5ppm/°C voltage reference with an optional external LTC6655 2.048V 5ppm/°C reference that is jumper selectable.
The default DAC configuration uses an internal 2.5V 3ppm/°C voltage reference with an optional external ADR4525 2.5V 2ppm/°C reference that is jumper selectable.
| VREF | Jumper Settings |
|---|---|
| ADC_VREF | Short P5 |
| DAC_VREF | Short P4 |
Power Supply Considerations and Configuration
All power for the CN0584 is provided by the CN0585 through the AFE connector. The CN0584 uses the +15 V and -15 V rails to provide the positive and negative supply voltages for the ADG5421F input protection switches. The +12 V and -12 V rails provide the positive and negative supply voltages for the ADA4898-1 ADC buffer amplifiers. The +3.3 V rail powers the EEPROM circuit. The power rails used in the hardware in the loop low latency development kit include:
| Power Rail | Description |
|---|---|
| +12 V | LT3045-1 provides the 12V rail supplying up 280mA |
| -12 V | LT3094 provides the -12V rail supplying up to -280mA |
| +15 V | LTM8049 provides the +15V rail at 80% efficiency |
| -15 V | LTM8049 provides the -15V rail at 80% efficiency |
| +3.3 V | Fed through from the FPGA FMC connector to the AFE connector |
System Setup Using a Zed Board
The EVAL-CN0584-EBZ is fully supported using a Zedboard.
Demo Requirements
The following is a list of items needed in order to replicate this demo.
- Hardware
- ZedBoard Rev D or later board
- 12Vdc, 3A power supply
- 16GB (or larger) Class 10 (or faster) micro-SD card
- Micro-USB cable
- User interface setup (choose one):
- HDMI monitor, keyboard, mouse plugged directly into the Zedboard
- Host Windows/Linux/Mac computer on the same network as the Zedboard
- Software
Loading Image on SD Card
In order to boot the Zedboard and control the EVAL-CN0584-EBZ, you will need to install ADI Kuiper Linux on an SD card. Complete instructions, including where to download the SD card image, how to write it to the SD card, and how to configure the system are provided on the Kuiper Linux page.
Configuring the SD Card
Follow the configuration procedure under Configuring the SD Card for FPGA Projects on the Kuiper Linux page. Copy the following files onto the boot directory to configure the SD card:
- uImage file for Zynq
- BOOT.BIN specific to your EVAL-CN0585-FMCZ + ZedBoard
- devicetree.dtb for Zynq specific to your EVAL-CN0585-FMCZ + ZedBoard
Setting up the Hardware
You will need to:
- Insert the SD-CARD into the SD Card Interface Connector (J12).
- Connect the EVAL-CN0585-FMCZ board into the ZedBoard FMC connector.
- Connect USB UART J14 (Micro USB) to your host PC.
- Plug your ethernet cable into the RJ45 ethernet connector(J11).
- Plug the Power Supply into the 12V Power input connector (J20) (DO NOT turn the device on).
- Set the jumpers as seen in the below picture:
- Loopback the DAC's output channels to the ADC's inputs as seen in the below picture:
- Turn it on.
- Wait ~30 seconds for the “DONE” LED to turn blue. This is near the DISP1.
All the products described on this page include ESD (electrostatic discharge) sensitive devices. Electrostatic charges as high as 4000V readily accumulate on the human body or test equipment and can discharge without detection.
Although the boards feature ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. This includes removing static charge on external equipment, cables, or antennas before connecting to the device.
Application Software (both locally and remotely on the FPGA)
Hardware Connection
The Libiio is a library used for interfacing with IIO devices and is required to be installed on your computer.
Download and Install the latest Libiio package on your machine.
To be able to connect your device, the software must be able to create a context. The context creation in the software depends on the backend used to connect to the device as well as the platform where the EVAL-CN0584-EBZ is attached. The Zedboard running ADI Kuiper Linux is currently the only platform supported for the CN0584. The user needs to supply a URI which will be used in the context creation.
The iio_info command is a part of the libIIO package that reports all IIO attributes.
Upon installation, simply enter the command on the terminal command line to access it.
For FPGA Direct Local Access:
iio_info
For Windows machine connected to an FPGA:
iio_info -u ip:<ip address of your ip>
Example:
- If your Zedboard has the IP address 192.168.1.7, you have to use iio_info -u ip::192.168.1.7 as your URI
Do note that the Windows machine and the FPGA board should be connected to the same network in order for the machine to detect the device.
IIO Oscilloscope
Make sure to download/update to the latest version of IIO-Oscilloscope found on this linkhttps://github.com/analogdevicesinc/iio-oscilloscope/releases
- Once done with the installation or an update of the latest IIO-Oscilloscope, open the application. The user needs to supply a URI which will be used in the context creation of the IIO Oscilloscope and the instructions can be seen in the previous section.
- Press refresh to display available IIO Devices and press connect.
- After the board is connected set the raw value to 1 for the following output voltages of the one-bit-adc-dac device which is the controller for the MAX7301ATL+ I/O Expander. This step will configure the value for the following pins which are connected to the MAX7301ATL+ I/O Expander:
| one-bit-adc-dac device channel | Schematic PIN |
|---|---|
| Voltage0 | GPIO0_VIO |
| Voltage1 | GPIO1_VIO |
| Voltage2 | GPIO2_VIO |
| Voltage3 | GPIO3_VIO |
| Voltage4 | GPIO6_VIO |
| Voltage5 | GPIO7_VIO |
| Voltage6 | PAD_ADC0 |
| Voltage7 | PAD_ADC1 |
| Voltage8 | PAD_ADC2 |
| Voltage9 | PAD_ADC3 |
- Select the desired input source for both AD3552R devices.
Even if the input source is set to adc_input or ramp_input the steps regarding the DAC Data Management tab have to be followed.
- Select the desired output range for both AD3552R devices.
Make sure you don't try to read/write the output_range attribute when the stream_status is in start_stream or start_stream_synced.
- From the DAC Data Manager Window select the output channels of the DAC and enable the cyclic buffer.
- Load an example file from the IIO Oscilloscope/lib/osc/waveforms folder.
If the source is set as dma_input and the data from all 4 channels needs to be synchronized make sure that you press the load button for the axi-ad3552r-1 device first then for axi-ad3552r-0.
- Click on the load button.
If the source is set as dma_input and the data from all 4 channels needs to be synchronized make sure that you write the start_stream_synced for the axi-ad3552r-1 device first then for axi-ad3552r-0.
- Select the stream_status IIO Attribute and start the stream (start_stream_synced means that all 4 channels are updated at the same time and the data streaming process waits for both DACs to be started).
If the source is set as dma_input and the data from all 4 channels needs to be synchronized make sure that you write the start_stream_synced for the
axi-ad3552r-1 device first then for axi-ad3552r-0.
- After the stream_status has been written you should see the data capture window:
Note that there is a phase delay between voltage0/voltage2 and voltage1/voltage3 because the DAC device channels are updated consecutively See the DAC UPDATE MODES section in AD3552R Data Sheet.
If you intend to stop the stream transmission and start it again synchronized set the stream_status IIO Attribute to stop_stream for axi-ad3552r-1 device first then for the axi-ad3552r-0 device.
PyADI-IIO
PyADI-IIO is a Python abstraction module for ADI hardware with IIO drivers to make them easier to use. This module provides device-specific APIs built on top of the current libIIO Python bindings. These interfaces try to match the driver naming as much as possible without the need to understand the complexities of libIIO and IIO.
Follow the step-by-step procedure on how to install, configure, and set up PYADI-IIO and install the necessary packages/modules needed by referring to this link.
Running the example
Github link for the Python sample script: CN0585 Python Example
After installing and configuring PYADI-IIO on your machine, you are now ready to run Python script examples. In our case, run the cn0585_fmcz_example.py found in the examples folder.
D:\pyadi-iio>export PYTHONPATH=D:/pyadi-iio/ D:\pyadi-iio>python examples/cn0585_fmcz_example.py ip:your_board_ip
Press enter and you will get these readings:
$ python examples/cn0585_fmcz_example.py uri: ip:your_board_ip ############# EEPROM INFORMATION ############ read 256 bytes from /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-1/1-0050/eeprom Date of Man : Fri Jan 20 08:11:00 2023 Manufacturer : Analog Devices Product Name : LLDK-LTC2387-AD3552R Serial Number : 56864654 Part Number : 1234 FRU File ID : 12131321 PCB Rev : VB PCB ID : HIL BOM Rev : VC Uses LVDS : Y ############################################# GPIO4_VIO state is: 0 GPIO5_VIO state is: 0 Voltage monitor values: Channel : temp0 : 49.25 Deg. C Channel : voltage0 : 2.26745605283 V Channel : voltage1 : 0.6274414057359999 V Channel : voltage2 : 2.061157224874 V Channel : voltage3 : 0.7531738275079999 V Channel : voltage4 : 2.092285154536 V Channel : voltage5 : 2.084960935792 V Channel : voltage6 : 2.2534179669039998 V Channel : voltage7 : 1.80969238133 V AXI4-Lite 0x108 register value: 0x2 AXI4-Lite 0x10c register value: 0xB Sample data min: 0 Sample data max: 65535 input_source:dac0: adc_input input_source:dac1: adc_input Maximum measured voltage 0 : 10.115187500000001 Maximum measured voltage 1 : 0.00103125 Maximum measured voltage 2 : 0.00034375000000000003 Maximum measured voltage 3 : 0.00103125 Minimum measured voltage 0: 10.107625 Minimum measured voltage 1: -0.00034375000000000003 Minimum measured voltage 2: -0.00103125 Minimum measured voltage 3: -0.00034375000000000003
The following window will pop up:
If you plan to transmit multiple cycles of synchronous stream, make sure axi-ad3552r-1 is started/stopped first, then axi-ad3552r-0.
MATLAB and Simulink
Required MATLAB Add-Ons:
Github link for the Matlab sample script: CN0585StreamingTest.m
The steps described in the Analog Devices Transceiver Toolbox For MATLAB and Simulink page have to be followed to configure the Matlab/Simulink project using the MathWorks HDL Workflow Advisor.
Device Control and Data Streaming
Remote data streaming to and from hardware is made available through system object interfaces, which are unique for each component or platform. The hardware interfacing system objects provide a class to both configure a given platform and move data back and forth from the device. After running the CN0585StreamingTest.m example The following window will pop up:
This is the terminal output that can be observed if the HDL Targeting with HDL-Coder flow was followed and there are 2 AXI4-Lite registers in the HDL DUT IP:
If you plan to transmit multiple cycles of synchronous stream, make sure axi-ad3552r-1 is started/stopped first, then axi-ad3552r-0.
HDL Targeting with HDL-Coder
Precision Toolbox supports the IP Core generation flow from MathWorks which allows for automated integration of DSP into HDL reference designs from Analog Devices. This workflow will take Simulink subsystems, run HDL-Coder to generate source Verilog, and then integrate that into a larger reference design.
Transmit reference design (Tx)
| Interface signal name | Width | Description |
|---|---|---|
| CN0584 ADC Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. |
| CN0584 ADC Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. |
| CN0584 ADC Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. |
| CN0584 ADC Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. |
| IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. |
| CN0584 DAC Data 0 OUT | 16 | AD3552R_0 DAC 0 channel data. To be used as input into the AD3552R interface IP. |
| CN0584 DAC Data 1 OUT | 16 | AD3552R_0 DAC 1 channel data. To be used as input into the AD3552R interface IP. |
| CN0584 DAC Data 2 OUT | 16 | AD3552R_1 DAC 0 channel data. To be used as input into the AD3552R interface IP. |
| CN0584 DAC Data 3 OUT | 16 | AD3552R_1 DAC 1 channel data. To be used as input into the AD3552R interface IP. |
| IP Data Valid OUT | 1 | Output signal that has to be logic '1' for a clock cycle period when the data starts to be valid. |
| IP Load Tx Data OUT | 1 | Custom IP output signal used to notify the design that the IP is ready to receive new input data. The duration must be 1 clock cycle. |
HDL Block diagram for Tx Reference design
Receive reference design (Rx)
| Interface signal name | Width | Description |
|---|---|---|
| IP Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. |
| IP Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. |
| IP Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. |
| IP Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. |
| IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. |
| IP Data 0 OUT | 16 | ADAQ23876 ADC 0 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 1 OUT | 16 | ADAQ23876 ADC 1 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 2 OUT | 16 | ADAQ23876 ADC 2 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 3 OUT | 16 | ADAQ23876 ADC 3 channel data. To be used as input for the ADC CPAK IP. |
| IP Data Valid OUT | 1 | Output signal that has to be logic '1' for a clock cycle period when the data starts to be valid. |
HDL Block diagram for Rx Reference design
Transmit and Receive reference design (Tx & Rx)
| Interface signal name | Width | Description |
|---|---|---|
| IP Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. |
| IP Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. |
| IP Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. |
| IP Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. |
| CN0584 ADC Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. |
| CN0584 ADC Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. |
| CN0584 ADC Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. |
| CN0584 ADC Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. |
| IP Valid Rx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. |
| IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. |
| IP Data 0 OUT | 16 | ADAQ23876 ADC 0 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 1 OUT | 16 | ADAQ23876 ADC 1 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 2 OUT | 16 | ADAQ23876 ADC 2 channel data. To be used as input for the ADC CPAK IP. |
| IP Data 3 OUT | 16 | ADAQ23876 ADC 3 channel data. To be used as input for the ADC CPAK IP. |
| CN0584 DAC Data 0 OUT | 16 | AD3552R_0 DAC 0 channel data. To be used as input into the AD3552R interface IP. |
| CN0584 DAC Data 1 OUT | 16 | AD3552R_0 DAC 1 channel data. To be used as input into the AD3552R interface IP. |
| CN0584 DAC Data 2 OUT | 16 | AD3552R_1 DAC 0 channel data. To be used as input into the AD3552R interface IP. |
| CN0584 DAC Data 3 OUT | 16 | AD3552R_1 DAC 1 channel data. To be used as input into the AD3552R interface IP. |
| IP Data Valid OUT | 1 | Output signal that has to be logic '1' for a clock cycle period when the data starts to be valid. |
| IP Load Tx Data OUT | 1 | Custom IP output signal used to notify the design that the IP is ready to receive new input data. The duration must be 1 clock cycle. |
HDL Block diagram for Tx and Rx Reference design
Schematic, PCB Layout, Bill of Materials
EVAL-CN0584-EBZ Design & Integration Files
- Schematics
- PCB Layout
- Bill of Materials
- Allegro Project
Additional Information and Useful Links
Reference Demos & Software
Hardware Registration
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resources/eval/user-guides/circuits-from-the-lab/cn0584.1685349842.txt.gz · Last modified: 29 May 2023 10:44 by Paul Pop