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resources:eval:user-guides:circuits-from-the-lab:cn0584 [29 May 2023 10:44] Paul Pop [Additional Information and Useful Links] |
resources:eval:user-guides:circuits-from-the-lab:cn0584 [31 May 2023 10:39] Paul Pop [MATLAB and Simulink] |
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| ==== MATLAB and Simulink ==== | ==== MATLAB and Simulink ==== | ||
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| <WRAP round download> | <WRAP round download> | ||
| Required MATLAB Add-Ons: | Required MATLAB Add-Ons: | ||
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| |< 100% 15% 5% 80% >| | |< 100% 15% 5% 80% >| | ||
| ^ Interface signal name ^ Width ^ Description ^ | ^ Interface signal name ^ Width ^ Description ^ | ||
| - | | CN0584 ADC Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. | | + | | IP Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. | |
| - | | CN0584 ADC Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. | | + | | IP Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. | |
| - | | CN0584 ADC Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. | | + | | IP Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. | |
| - | | CN0584 ADC Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. | | + | | IP Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. | |
| | IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. | | | IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. | | ||
| - | | CN0584 DAC Data 0 OUT | 16 | AD3552R_0 DAC 0 channel data. To be used as input into the AD3552R interface IP. | | + | | CN0585 DAC Data 0 OUT | 16 | AD3552R_0 DAC 0 channel data. To be used as input into the AD3552R interface IP. | |
| - | | CN0584 DAC Data 1 OUT | 16 | AD3552R_0 DAC 1 channel data. To be used as input into the AD3552R interface IP. | | + | | CN0585 DAC Data 1 OUT | 16 | AD3552R_0 DAC 1 channel data. To be used as input into the AD3552R interface IP. | |
| - | | CN0584 DAC Data 2 OUT | 16 | AD3552R_1 DAC 0 channel data. To be used as input into the AD3552R interface IP. | | + | | CN0585 DAC Data 2 OUT | 16 | AD3552R_1 DAC 0 channel data. To be used as input into the AD3552R interface IP. | |
| - | | CN0584 DAC Data 3 OUT | 16 | AD3552R_1 DAC 1 channel data. To be used as input into the AD3552R interface IP. | | + | | CN0585 DAC Data 3 OUT | 16 | AD3552R_1 DAC 1 channel data. To be used as input into the AD3552R interface IP. | |
| - | | IP Data Valid OUT | 1 | Output signal that has to be logic '1' for a clock cycle period when the data starts to be valid. | | + | | IP Load Tx Data OUT | 1 | Custom IP output signal used to notify the design that the IP is ready to receive new input data. Output signal that has to be logic '1' for a clock cycle period when the data starts to be valid. | |
| - | | IP Load Tx Data OUT | 1 | Custom IP output signal used to notify the design that the IP is ready to receive new input data. The duration must be 1 clock cycle. | | + | |
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| |< 100% 15% 5% 80% >| | |< 100% 15% 5% 80% >| | ||
| ^ Interface signal name ^ Width ^ Description ^ | ^ Interface signal name ^ Width ^ Description ^ | ||
| - | | IP Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. | | + | | CN0585 ADC Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. | |
| - | | IP Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. | | + | | CN0585 ADC Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. | |
| - | | IP Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. | | + | | CN0585 ADC Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. | |
| - | | IP Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. | | + | | CN0585 ADC Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. | |
| - | | IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. | | + | | IP Valid Rx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. | |
| | IP Data 0 OUT | 16 | ADAQ23876 ADC 0 channel data. To be used as input for the ADC CPAK IP. | | | IP Data 0 OUT | 16 | ADAQ23876 ADC 0 channel data. To be used as input for the ADC CPAK IP. | | ||
| | IP Data 1 OUT | 16 | ADAQ23876 ADC 1 channel data. To be used as input for the ADC CPAK IP. | | | IP Data 1 OUT | 16 | ADAQ23876 ADC 1 channel data. To be used as input for the ADC CPAK IP. | | ||
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| | IP Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. | | | IP Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. | | ||
| | IP Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. | | | IP Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. | | ||
| - | | CN0584 ADC Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. | | + | | CN0585 ADC Data 0 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_0 IP ADC DATA port in the ADI reference design. | |
| - | | CN0584 ADC Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. | | + | | CN0585 ADC Data 1 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_1 IP ADC DATA port in the ADI reference design. | |
| - | | CN0584 ADC Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. | | + | | CN0585 ADC Data 2 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_2 IP ADC DATA port in the ADI reference design. | |
| - | | CN0584 ADC Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. | | + | | CN0585 ADC Data 3 IN | 16 | Custom IP data input signal. This signal is connected to the AXI_LTC2387_3 IP ADC DATA port in the ADI reference design. | |
| | IP Valid Rx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. | | | IP Valid Rx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. | | ||
| | IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. | | | IP Valid Tx Data IN | 1 | Input signal that has logic 1 value for a clock cycle period when the data starts to be valid. | | ||
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| | IP Data 2 OUT | 16 | ADAQ23876 ADC 2 channel data. To be used as input for the ADC CPAK IP. | | | IP Data 2 OUT | 16 | ADAQ23876 ADC 2 channel data. To be used as input for the ADC CPAK IP. | | ||
| | IP Data 3 OUT | 16 | ADAQ23876 ADC 3 channel data. To be used as input for the ADC CPAK IP. | | | IP Data 3 OUT | 16 | ADAQ23876 ADC 3 channel data. To be used as input for the ADC CPAK IP. | | ||
| - | | CN0584 DAC Data 0 OUT | 16 | AD3552R_0 DAC 0 channel data. To be used as input into the AD3552R interface IP. | | + | | CN0585 DAC Data 0 OUT | 16 | AD3552R_0 DAC 0 channel data. To be used as input into the AD3552R interface IP. | |
| - | | CN0584 DAC Data 1 OUT | 16 | AD3552R_0 DAC 1 channel data. To be used as input into the AD3552R interface IP. | | + | | CN0585 DAC Data 1 OUT | 16 | AD3552R_0 DAC 1 channel data. To be used as input into the AD3552R interface IP. | |
| - | | CN0584 DAC Data 2 OUT | 16 | AD3552R_1 DAC 0 channel data. To be used as input into the AD3552R interface IP. | | + | | CN0585 DAC Data 2 OUT | 16 | AD3552R_1 DAC 0 channel data. To be used as input into the AD3552R interface IP. | |
| - | | CN0584 DAC Data 3 OUT | 16 | AD3552R_1 DAC 1 channel data. To be used as input into the AD3552R interface IP. | | + | | CN0585 DAC Data 3 OUT | 16 | AD3552R_1 DAC 1 channel data. To be used as input into the AD3552R interface IP. | |
| | IP Data Valid OUT | 1 | Output signal that has to be logic '1' for a clock cycle period when the data starts to be valid. | | | IP Data Valid OUT | 1 | Output signal that has to be logic '1' for a clock cycle period when the data starts to be valid. | | ||
| | IP Load Tx Data OUT | 1 | Custom IP output signal used to notify the design that the IP is ready to receive new input data. The duration must be 1 clock cycle. | | | IP Load Tx Data OUT | 1 | Custom IP output signal used to notify the design that the IP is ready to receive new input data. The duration must be 1 clock cycle. | | ||
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| {{ :resources:eval:user-guides:circuits-from-the-lab:cn0585:rx_tx_configuration_lldk.png?600 }} | {{ :resources:eval:user-guides:circuits-from-the-lab:cn0585:rx_tx_configuration_lldk.png?600 }} | ||
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resources/eval/user-guides/circuits-from-the-lab/cn0584.txt · Last modified: 25 Sep 2023 21:46 by Rukiye Guldali