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CN0584 (Low Latency Development Kit) is a development platform consisting of two boards the EVAL-CN0585-FMCZ and the EVAL-CN0584-EBZ. EVAL-CN0585-FMCZ consists of 4 x 16-bit ADC channels and 4 x 16-bit DAC channels that are interfaced with an FPGA through the FMC Low Pin Count (LPC) Connector. Current revision of EVAL-CN0585-FMCZ is Rev B. EVAL-CN0584-EBZ is the application specific analog front end (AFE) board.CN0584 is connected to a Zedboard to build a development system setup like shown in Figure 7.
The Low Latency Development Kit (LLDK) provides a complete data acquisition and signal generation platform with on-board power rails, voltage monitoring, logic level translation, general purpose I/O, I2C, SPI, and a personality interface connector.
The key performance benefit of the LLDK system is the ability to perform a complete capture and conversion of precision analog input data in <70ns with the ADC module and generate a settled full-scale analog output in <200ns from initial data written to the DAC.
There are four channels of differential input signals on EVAL-CN0584-EBZ.
|Channel||Positive Input Signal||Negative Input Signal|
Table 1. ADC Input Signal Connectors
LLDK has configurable input voltage ranges of ±10 V(Default), ±5 V, ±4.096 V, ±2.5 V, and ±1.5 V. The input range can be changed by modifying resistor placements on EVAL-CN0584-EBZ as described in Table 2.
|Channel||Input Voltage Range||AFE Board Modification|
|Channel 0||±10 V (default)||Include R19A, R21A, R22A, R24A; DNI R18A, R20A, R23A, R25A|
|±5 V||Include R18A, R20A, R23A, R25A; DNI R19A, R21A, R22A, R24A|
|±4.096 V||Include R19A, R21A; DNI R18A, R20A, R22A, R23A, R24A, R25A|
|±2.5 V||Include R18A, R20A; DNI R19A, R21A, R22A, R23A, R24A, R25A|
|±1.5 V||Include R18A, R19A, R20A, R21A; DNI R22A, R23A, R24A, R25A|
|Channel 1||±10 V (default)||Include R19B, R21B, R22B, R24B; DNI R18B, R20B, R23B, R25B|
|±5 V||Include R18B, R20B, R23B, R25B; DNI R19B, R21B, R22B, R24B|
|±4.096 V||Include R19B, R21B; DNI R18B, R20B, R22B, R23B, R24B, R25B|
|±2.5 V||Include R18B, R20B; DNI R19B, R21B, R22B, R23B, R24B, R25B|
|±1.5 V||Include R18B, R19B, R20B, R21B; DNI R22B, R23B, R24B, R25B|
|Channel 2||±10 V (default)||Include R19C, R21C, R22C, R24C; DNI R18C, R20C, R23C, R25C|
|±5 V||Include R18C, R20C, R23C, R25C; DNI R19C, R21C, R22C, R24C|
|±4.096 V||Include R19C, R21C; DNI R18C, R20C, R22C, R23C, R24C, R25C|
|±2.5 V||Include R18C, R20C; DNI R19C, R21C, R22C, R23C, R24C, R25C|
|±1.5 V||Include R18C, R19C, R20C, R21C; DNI R22C, R23C, R24C, R25C|
|Channel 3||±10 V (default)||Include R19D, R21D, R22D, R24D; DNI R18D, R20D, R23D, R25D|
|±5 V||Include R18D, R20D, R23D, R25D; DNI R19D, R21D, R22D, R24D|
|±4.096 V||Include R19D, R21D; DNI R18D, R20D, R22D, R23D, R24D, R25D|
|±2.5 V||Include R18D, R20D; DNI R19D, R21D, R22D, R23D, R24D, R25D|
|±1.5 V||Include R18D, R19D, R20D, R21D; DNI R22D, R23D, R24D, R25D|
Table 2. ADC Input Voltage Range Selection by Resistor Connections
LLDK can support multiple output voltage ranges which can be configured, such as 0 to 2.5 V, 0 V to 5 V, −5 V to +5 V, and −10 V to +10 V, and custom intermediate ranges with full 16-bit resolution. In order to change the output range, resistor placements on the AFE board must be modified and register settings must be applied to AD3552R on EVAL-CN0585-FMCZ as described in Table 4.
Table 3. DAC Output Signal Connectors
|Channel||Output Span||VZS (V)||VFS (V)||AFE Board Modification||Register Setting|
|CH0||+/- 10V (Default)||-10.382||10.380||Include R9; DNI R10, R11||CH0_CH1_OUTPUT_RANGE = 0x100|
|+/- 5V||-5.165||5.166||Include R11; DNI R9, R10||CH0_CH1_OUTPUT_RANGE = 0x011|
|10V||-0.165||10.163||Include R11; DNI R9, R10||CH0_CH1_OUTPUT_RANGE = 0x010|
|5V||-0.078||5.077||Include R10; DNI R9, R11||CH0_CH1_OUTPUT_RANGE = 0x001|
|2.5V||-0.198||2.701||Include R10; DNI R9, R11||CH0_CH1_OUTPUT_RANGE = 0x000|
|CH1||+/- 10V (Default)||-10.382||10.380||Include R12; DNI R13, R14||CH0_CH1_OUTPUT_RANGE = 0x100|
|+/- 5V||-5.165||5.166||Include R13; DNI R12, R14||CH0_CH1_OUTPUT_RANGE = 0x011|
|10V||-0.165||10.163||Include R13; DNI R12, R14||CH0_CH1_OUTPUT_RANGE = 0x010|
|5V||-0.078||5.077||Include R14; DNI R12, R13||CH0_CH1_OUTPUT_RANGE = 0x001|
|2.5V||-0.198||2.701||Include R14; DNI R12, R13||CH0_CH1_OUTPUT_RANGE = 0x000|
|CH2||+/- 10V (Default)||-10.382||10.380||Include R15; DNI R16, R17||CH2_CH3_OUTPUT_RANGE = 0x100|
|+/- 5V||-5.165||5.166||Include R16; DNI R15, R17||CH2_CH3_OUTPUT_RANGE = 0x011|
|10V||-0.165||10.163||Include R16; DNI R15, R17||CH2_CH3_OUTPUT_RANGE = 0x010|
|5V||-0.078||5.077||Include R17; DNI R15, R16||CH2_CH3_OUTPUT_RANGE = 0x001|
|2.5V||-0.198||2.701||Include R17; DNI R15, R16||CH2_CH3_OUTPUT_RANGE = 0x000|
|CH3||+/- 10V (Default)||-10.382||10.380||Include R18; DNI R19, R20||CH2_CH3_OUTPUT_RANGE = 0x100|
|+/- 5V||-5.165||5.166||Include R19; DNI R18, R20||CH2_CH3_OUTPUT_RANGE = 0x011|
|10V||-0.165||10.163||Include R19; DNI R18, R20||CH2_CH3_OUTPUT_RANGE = 0x010|
|5V||-0.078||5.077||Include R20; DNI R18, R19||CH2_CH3_OUTPUT_RANGE = 0x001|
|2.5V||-0.198||2.701||Include R20; DNI R18, R19||CH2_CH3_OUTPUT_RANGE = 0x000|
Table 4. DAC Output Voltage Range Selection by Resistor Connections and Register Settings
The default ADC reference configuration uses the internal 2.048 V, ±0.1% accurate, 20 ppm/°C max voltage reference. For more stringent use cases where the accuracy and temperature drift is an issue, an external LTC6655 2.048 V, ±0.025% accurate, 2 ppm/°C max voltage reference can be used.
The default DAC reference configuration uses the internal 2.5 V, ±0.3% accurate, 10 ppm/°C max voltage reference. For more stringent use cases where the accuracy and temperature drift is an issue, an external ADR4525 2.5 V, ±0.02% accurate, 2 ppm/°C max voltage reference can be used.
Table 5. Voltage Reference Settings
All power for CN0584 is provided by EVAL-CN0585-FMCZ through the AFE connector. CN0584 uses the +15 V and -15 V rails to provide the positive and negative supply voltages for the ADG5421F input protection switches. The +12 V and -12 V rails provide the positive and negative supply voltages for the ADA4898-1 ADC buffer amplifiers. The +3.3 V rail powers the EEPROM circuit. Table 6 provides more details on LLDK power rails:
|+12 V||LT3045-1 provides the 12V rail supplying up 280mA|
|-12 V||LT3094 provides the -12V rail supplying up to -280mA|
|+15 V||LTM8049 provides the +15V rail at 80% efficiency|
|-15 V||LTM8049 provides the -15V rail at 80% efficiency|
|+3.3 V||Fed through from the FPGA FMC connector to the AFE connector|
Table 6. Power Rail Descriptions
CN0584 is fully supported using a ZedBoard.
Figure 4. EVAL-CN0585-FMCZ connected to EVAL-CN0584-EBZ
The following is a list of items needed for system setup:
The box includes a pre-programmed SD card. You can skip the steps in this section and go to the Setting up the Hardware section if using this provided card.
To boot the ZedBoard and control the EVAL-CN0585-FMCZ, you will need to install ADI Kuiper Linux on an SD card. Complete instructions, including where to download the SD card image, how to write it to the SD card, and how to configure the system are provided on the Kuiper Linux page.
Follow the configuration procedure under Configuring the SD Card for FPGA Projects on the Kuiper Linux page. Copy the following files onto the boot directory to configure the SD card (download link sdcard_config_files.zip):
You will need to:
All the products described on this page include ESD (electrostatic discharge) sensitive devices. Electrostatic charges as high as 4000V readily accumulate on the human body or test equipment and can discharge without detection.
Although the boards feature ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. This includes removing static charge on external equipment, cables, or antennas before connecting to the device.
The CN0584 can be interfaced with using IIO Oscilloscope, Python, or MATLAB to enable device configuration, capture of incoming samples from the ADCs, and generation of waveforms to be transmitted by the DACs.
Libiio is a library used for interfacing with IIO devices and must be installed on your computer to interface with the hardware.
Download and Install the latest Libiio package on your machine.
To connect to your device, the IIO Osciloscope software must be able to create a context. The context creation in the software depends on the backend used to connect to the device as well as the platform where the EVAL-CN0585-FMCZ is attached. The ZedBoard running ADI Kuiper Linux is currently the only platform supported for the CN0585.
The user needs to supply a URI (Uniform Resource Identifier) which will be used in the context creation. To get the URI, use the command iio_info in the terminal. The iio_info command is a part of the libIIO package that reports all IIO attributes.Upon installation, simply enter the command on the terminal command line to access it.
iio_info -u ip:<ip address of your ip>
IIO Oscilloscope is a cross platform GUI application which can interface with different evaluation boards from within a Linux system.
Figure 9. MAX7301ATL Output Channels Configuration
|one-bit-adc-dac device channel||Schematic PIN|
Table 7. Voltage Configuration for GPIO Pins
The CN0584 can be interfaced to Python using the PyADI-IIO. PyADI-IIO is a Python abstraction module to simplify interaction with IIO drivers on ADI hardware. This module provides device-specific APIs built on top of the current libIIO Python bindings. These interfaces try to match the driver naming as much as possible without the need to understand the complexities of libIIO and IIO.
Follow the step-by-step procedure on how to install, configure, and set up PyADI-IIO and install the necessary packages/modules needed by referring to PyADI-IIO.
Github link for the Python sample script: CN0585 Python Example
After installing and configuring PYADI-IIO on your machine, you are now ready to run Python script examples. To follow this example, run the cn0585_fmcz_example.py found in the examples folder.
D:\pyadi-iio>export PYTHONPATH=D:/pyadi-iio/ D:\pyadi-iio>python examples/cn0585_fmcz_example.py ip:your_board_ip
Press enter and lines below will be observed:
$ python examples/cn0585_fmcz_example.py uri: ip:your_board_ip ############# EEPROM INFORMATION ############ read 256 bytes from /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-1/1-0050/eeprom Date of Man : Fri Jan 20 08:11:00 2023 Manufacturer : Analog Devices Product Name : LLDK-LTC2387-AD3552R Serial Number : 56864654 Part Number : 1234 FRU File ID : 12131321 PCB Rev : VB PCB ID : HIL BOM Rev : VC Uses LVDS : Y ############################################# GPIO4_VIO state is: 0 GPIO5_VIO state is: 0 Voltage monitor values: Channel : temp0 : 49.25 Deg. C Channel : voltage0 : 2.26745605283 V Channel : voltage1 : 0.6274414057359999 V Channel : voltage2 : 2.061157224874 V Channel : voltage3 : 0.7531738275079999 V Channel : voltage4 : 2.092285154536 V Channel : voltage5 : 2.084960935792 V Channel : voltage6 : 2.2534179669039998 V Channel : voltage7 : 1.80969238133 V AXI4-Lite 0x108 register value: 0x2 AXI4-Lite 0x10c register value: 0xB Sample data min: 0 Sample data max: 65535 input_source:dac0: adc_input input_source:dac1: adc_input Maximum measured voltage 0 : 10.115187500000001 Maximum measured voltage 1 : 0.00103125 Maximum measured voltage 2 : 0.00034375000000000003 Maximum measured voltage 3 : 0.00103125 Minimum measured voltage 0: 10.107625 Minimum measured voltage 1: -0.00034375000000000003 Minimum measured voltage 2: -0.00103125 Minimum measured voltage 3: -0.00034375000000000003
The following window will pop up:
Required MATLAB Add-Ons:
Github link for the Matlab sample script: CN0585StreamingTest.m
The steps described in the Analog Devices Transceiver Toolbox For MATLAB and Simulink page have to be followed to configure the Matlab/Simulink project using the MathWorks HDL Workflow Advisor.
Remote data streaming to and from hardware is made available through system object interfaces, which are unique for each component or platform. The hardware interfacing system objects provide a class to both configure a given platform and move data back and forth from the device. After running the CN0585StreamingTest.m example as described in Steps for MATLAB Configuration of CN0585, the window in Figure 16 will pop up:
The ZedBoard that drives CN0585 is configured with a HDL reference design which is an embedded system built around a processor core either ARM, NIOS-II, or Microblaze. A functional block diagram of the system is shown in Figure 17.
The device digital interface is handled by specific device cores axi_ad35552r for the DAC path and axi_ltc2387 for the ADC path. The cores are programmable through an AXI-lite interface. HDL IP(HDL_DUT) code to be integrated in this reference design is generated using High Speed Converter Toolbox. (https://github.com/analogdevicesinc/HighSpeedConverterToolbox/). High Speed Converter Toolbox supports the IP Core generation flow from MathWorks which allows for automated integration of DSP into HDL reference designs from Analog Devices. The workflow for generating HDL_DUT codes takes Simulink subsystems, runs HDL-Coder to generate source Verilog, and then integrates that into a larger reference design. HDL_DUT Code Generation Workflow is described in configuring_lldk.pdf. HDL_DUT with Configuration Registers (Accessed over AXI-Lite Interface) Code Generation Workflow for Transmit Configuration is described in configuring_lldk_axi_lite.pdf