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CN0577 HDL Reference Design


The CN0577 provides an analog front-end and an FMC digital interface for LTC2387-18, its core. It is a low noise, high speed successive approximation register (SAR) ADC with a resolution of 18 bits and sampling rate up to 15MSPS.

CN0577 includes an on-board reference oscillator and a retiming circuit to minimize signal-to-noise ratio (SNR) degradation due to the FPGA additive jitter.

In order to support high speed operations while minimizing the number of data lines, a serial LVDS digital interface is used. It has a one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application, through setting a parameter.

More details about ADI reference designs architecture here.

Evaluation board

Supported FPGA carriers

HDL Design Description

In the master version, the TWOLANES parameter is set to 1, so it works only in two-lane output mode.
The VADJ for the Zedboard must be set to 2.5V!

The PD and TESTPAT parameters are tied to GPIOs (33 and 32 respectively) so they can be configured by the software.

The conversion starts when a rising edge is detected on the CNV signal. This signal is generated by the AXI_PWM_GEN core, alongside with a clk_gate signal.

Block Diagram


The only parameter that can be changed so far, is TWOLANES. It specifies whether the two-lane output mode is activated or not. When activated, the ADC outputs two bits at the same time, on DA+/DA- and DB+/DB-. When it is low, then DB+/DB- is disabled.

By default, it is set to 1 here and passed further through the board design file here.

PL interrupts

When developing the Linux software parts for an HDL project, the interrupts number to the PS have a different number in the software side. More details here.

Interr. name HDL interr. Linux Zynq Actual Zynq
axi_ltc2387_dma 13 57 89

GPIO signals

PS7 EMIO offset = 54

pd_cntrl 87 33
testpat_cntrl 86 32

I/O Interface

Interface Pin Type Description
Core clock
ref_clk_* input LVDS clock input
LVDS ADC interface
clk_* output LVDS output clock going to the chip, to serially shift out the conversion result
dco_* input LVDS data clock input
da_* input Serial LVDS data input
db_* input Serial LVDS data input
cnv_* output Conversion start LVDS
cnv_en output Conversion enable, used as clear signal for the retiming flop from the chip (see schematic)
pd_cntrl output Powerdown control signal
testpat_cntrl output Enable for testing with a predefined pattern
twolanes_cntrl output Selection between one-lane mode and two-lane mode. Default it is 1

Clock Architecture

The clock architecture of the CN0577 is designed with careful consideration to ensure low jitter and low phase noise.

An on-board 120 MHz voltage controlled crystal oscillator (VCXO) is used to provide the clock for the CN0577 board and the FPGA. It is further named as reference clock. This clock is gated and fed back to the device as the sampling clock, on which the data was sampled.

The DMA runs on the ZynqPS clock FCLK_CLK0 which has a frequency of 100MHz.

Digital Interface

The digital interface consists of the following signals:

  • ref_clk_* - LVDS clock input, used as reference clock for the system, after it is converted to single-ended signal by ad_data_clk module
  • clk_* - LVDS clock coming from the FPGA, that serially shifts out the conversion result
  • dco_* - LVDS clock input
  • da_* - serial LVDS data input
  • db_* - serial LVDS data input
  • cnv_* - conversion start LVDS; a rising edge starts the conversion cycle
  • cnv_en - signal that is used as CLR_N for the retiming flop from inside the CN0577 board
  • pd_cntrl - exposed on GPIO 33
  • testpat_cntrl - exposed on GPIO 32
  • twolanes_cntrl - hardcoded to 1 to always be used in two-lane mode

ADC Timing Characteristics

The timing considerations specified in the datasheet of the LTC2387-18 were taken in consideration, and are implemented in the constraints file of the project.

What must be noted, is that the cnv_en signal must be constrained in order to meet timing requirements for tCYC, tCONV, based on tFIRSTCLK and tLASTCLK. cnv_en being a CLR_N of the retiming flop, forces us to simulate the clock of the retiming flop.

In other words, a virtual clock is created, being a shadow of ref_clk_* (LVDS_CLK in schematic), and because it comes from the output of the local oscillator, it needs to be shifted with the propagation delay that is given from passing the level translator. Thus, it is shifted with 0.225ns compared to the ref_clk_* signal.

Connector and Jumper Configurations

Depending on what configuration of pins is chosen on the jumpers P1, P2 and P3, the device can act in different modes, as described below.

The PD_N and TESTPAT jumpers must be disconnected because the signals are tied to GPIOs! By default, TWOLANES is set to 1 in HDL code!

Of course, the PD jumper overrides the PD signal from the FPGA. It is controlled by a one-bit-adc-dac, in software.

  • P1 - configures PD_N
    • Shorting pins 1 and 2 → PD_N = 1, device is not powered down
    • Shorting pins 2 and 3 → PD_N = 0, device is powered down
  • P2 - configures TESTPAT
    • Shorting pins 1 and 2 → TESTPAT = 1, pattern testing is active
    • Shorting pins 2 and 3 → TESTPAT = 0, pattern testing is inactive
  • P3 - configures TWOLANES parameter
    • Shorting pins 1 and 2 → TWOLANES = 1 (TWO LANES mode)
    • Shorting pins 2 and 3 → TWOLANES = 0 (ONE LANE mode)

The FMC connector connects to the LPC connector of the carrier board.


The software parts for this IP core can be found at:


resources/eval/user-guides/circuits-from-the-lab/cn0577/hdl.1673884018.txt.gz · Last modified: 16 Jan 2023 16:46 by Iulia Moldovan