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resources:eval:user-guides:circuits-from-the-lab:cn0577:hdl [22 Sep 2022 19:07] – Correct explanations Iulia Moldovanresources:eval:user-guides:circuits-from-the-lab:cn0577:hdl [22 Feb 2023 12:54] (current) – Add Circuit Note page Iulia Moldovan
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 In order to support high speed operations while minimizing the number of data lines, a serial LVDS digital interface is used. It has a one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application, through setting a parameter. \\ In order to support high speed operations while minimizing the number of data lines, a serial LVDS digital interface is used. It has a one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application, through setting a parameter. \\
  
 +More details about ADI reference designs architecture [[:resources:fpga:docs:arch|here]].
  
 ===== Evaluation board ===== ===== Evaluation board =====
-  * [[ |CN0577 Circuit Note Page]]+  * [[adi>media/en/reference-design-documentation/reference-designs/cn0577.pdf |CN0577 Circuit Note Page]]
   * [[adi>LTC2387-18|LTC2387-18]] chip   * [[adi>LTC2387-18|LTC2387-18]] chip
  
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 ===== HDL Design Description ===== ===== HDL Design Description =====
 <note important>In the master version, the TWOLANES parameter is set to 1, so it works only in two-lane output mode.</note> <note important>In the master version, the TWOLANES parameter is set to 1, so it works only in two-lane output mode.</note>
 +
 +<note important>The VADJ for the Zedboard must be set to 2.5V!</note>
  
 The PD and TESTPAT parameters are tied to GPIOs (33 and 32 respectively) so they can be configured by the software. The PD and TESTPAT parameters are tied to GPIOs (33 and 32 respectively) so they can be configured by the software.
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 By default, it is set to 1 [[repo>hdl/tree/master/projects/cn0577/zed/system_bd.tcl#L2|here]] and passed further through the board design file [[repo>hdl/tree/master/projects/cn0577/common/cn0577_bd.tcl#L19|here]]. By default, it is set to 1 [[repo>hdl/tree/master/projects/cn0577/zed/system_bd.tcl#L2|here]] and passed further through the board design file [[repo>hdl/tree/master/projects/cn0577/common/cn0577_bd.tcl#L19|here]].
 +
 +=== PL interrupts ===
 +
 +When developing the Linux software parts for an HDL project, the interrupts number to the PS have a different number in the software side.
 +More details [[:resources:fpga:docs:arch#interrupts|here]].
 +
 +^Interr. name ^HDL interr. ^Linux Zynq ^Actual Zynq ^
 +|  axi_ltc2387_dma  |  13  |  57  |  89  |
 +
 +=== GPIO signals ===
 +
 +PS7 EMIO offset = 54
 +
 +^GPIO HDL name   ^GPIO nb. ^HDL GPIO nb.^
 +| pd_cntrl | 87 | 33 |
 +| testpat_cntrl | 86 | 32 |
  
  
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 Depending on what configuration of pins is chosen on the jumpers P1, P2 and P3, the device can act in different modes, as described below. Depending on what configuration of pins is chosen on the jumpers P1, P2 and P3, the device can act in different modes, as described below.
-<note>+<note important>
 The PD_N and TESTPAT jumpers must be disconnected because the signals are tied to GPIOs! The PD_N and TESTPAT jumpers must be disconnected because the signals are tied to GPIOs!
 By default, TWOLANES is set to 1 in HDL code! By default, TWOLANES is set to 1 in HDL code!
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     * Shorting pins 1 and 2 -> TWOLANES = 1 (TWO LANES mode)     * Shorting pins 1 and 2 -> TWOLANES = 1 (TWO LANES mode)
     * Shorting pins 2 and 3 -> TWOLANES = 0 (ONE LANE mode)     * Shorting pins 2 and 3 -> TWOLANES = 0 (ONE LANE mode)
- 
-==== FMC Connector ==== 
  
 The FMC connector connects to the LPC connector of the carrier board. The FMC connector connects to the LPC connector of the carrier board.
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   * Wiki page for [[:resources:fpga:docs:axi_ltc2387|AXI_LTC2387]]   * Wiki page for [[:resources:fpga:docs:axi_ltc2387|AXI_LTC2387]]
   * Schematic: [[ |CN0577 schematic]]   * Schematic: [[ |CN0577 schematic]]
 +  * [[:resources:fpga:docs:arch|HDL Architecture]]
resources/eval/user-guides/circuits-from-the-lab/cn0577/hdl.1663866440.txt.gz · Last modified: 22 Sep 2022 19:07 by Iulia Moldovan

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