This version is outdated by a newer approved version.
This version (22 Aug 2022 18:42) is a draft.
Approvals: 0/1
This version (22 Aug 2022 18:42) is a draft.Approvals: 0/1
This is an old revision of the document!
Table of Contents
CN0577 HDL Reference Design
Introduction
The CN0577 provides an analog front-end and an FMC digital interface for LTC2387-18, its core.
This core is a low noise, high speed successive approximation register (SAR) ADC with a resolution of 16-/18-bit and sampling rate up to 15MSPS. CN0577 includes an on-board reference oscillator and a retiming circuit to minimize signal-to-noise ratio (SNR) degradation due to the FPGA additive jitter.
In order to support high speed operations while minimizing the number of data lines, a serial LVDS digital interface is used. It has a one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application, through setting a parameter.
Evaluation board
Supported FPGA carriers
HDL Design Description
In the master version, the TWOLANES parameter is set to 1, so it works only in two-lane output mode.
The PD and TESTPAT parameters are tied to GPIOs (33 and 32 respectively) so they can be configured by the software.
The conversion starts when a rising edge is detected on the CNV signal. This signal is generated by the AXI_PWM_GEN core, alongside with a clk_gate signal which is used to output the ADC data
After the CN0577 is powered on or exits power-down mode, conversion data is invalid for the first two conversion cycles, thus the CNV signal has the offset parameter from AXI_PWM_GEN set to 1 (to delay it with two clock cycles)
Block Diagram
Clock Architecture
The clock architecture of the CN0577 is designed with careful consideration to ensure low jitter and low phase noise.
An on-board 120 MHz voltage controlled crystal oscillator (VCXO) is used to provide the clock for the CN0577 reference design board and the FPGA. It is further named as *reference clock*. This clock is fed back to the device as the *sampling clock*, on which the data was sampled.
The DMA runs on the ZynqPS clock FCLK_CLK0 which has a frequency of 100MHz.
Digital Interface
Analog Input
Power
Connector and Jumper Configurations
Depending on what configuration of pins is chosen on the jumpers P1, P2 and P3, the device can act in different modes, as described below.
The PD_N and TESTPAT jumpers must be disconnected because the signals are tied to GPIOs!
By default, TWOLANES is set to 1 in HDL code!
Of course, the PD jumper overrides the PD signal from the FPGA. It is controlled by a one-bit-adc-dac, in software.
- P1 - configures PD_N (powerdown signal that is active on 0)
- Shorting pins 1 and 2 → PD_N = 1 (inactive), meaning the device is not powered down
- Shorting pins 2 and 3 → PD_N = 0 (active), meaning the device is powered down
- P2 - configures TESTPAT
- Shorting pins 1 and 2 → TESTPAT = 1, meaning that the pattern testing is active
- Shorting pins 2 and 3 → TESTPAT = 0, meaning that the pattern testing is inactive
- P3 - configures TWOLANES parameter
- Shorting pins 1 and 2 → TWOLANES = 1 (meaning it is active in TWO LANES mode)
- Shorting pins 2 and 3 → TWOLANES = 0 (meaning it is active in ONE LANE mode)
FMC Connector
The FMC connector connects to the LPC connector of the carrier board.
Software
SD card setup (point to Kuiper wiki page)
IIO_Info
IIO_Oscilloscope
Resources
- HDL reference design: CN0577 HDL project on GitHub
- Linux sources: CN0577 devicetree and CN0577 Linux Kernel driver
- Schematic: CN0577 schematic
resources/eval/user-guides/circuits-from-the-lab/cn0577/hdl.1661186557.txt.gz · Last modified: 22 Aug 2022 18:42 by Iulia Moldovan