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Instrumentation applications such as flow cytometry, optical pulse measurement, fast control loops, fast digital distortion correction, and image sensor digitization present unique data acquisition challenges. These applications often require a combination of high sample rate, high linearity, low drift, low noise, and low latency.
The EVAL-CN0577-FMCZ is an 18-bit, 15 MSPS, 2 ppm linear data acquisition system with an easy to drive input impedance of 1.1 kΩ. The analog input range is 8.096 V peak-to-peak and can be driven in either single-ended or differential mode, providing flexibility for many different applications.
The circuit is in field programmable gate array (FPGA) mezzanine card (FMC) form factor, powered with 12 V either from the FMC connector or an external supply. The digital interface uses serial low voltage differential signaling (LVDS), minimizing the input/output requirements and enabling easy integration with other FPGA designs
A separate data clock eases the timing requirements of the host FPGA. An on-board 120 MHz clock is forwarded to the FPGA and a CONVERT retiming flip-flop reduces jitter from the convert signal of the FPGA.
|P1||Power Down (PD) Mode||When PD is high CN0577 will operate normally, but when PD is low CN0577 board enters power-down mode and all circuitry (including LVDS interface) is shutdown.||PD = High (Pins 1 and 2) PD = Low (Pins 2 and 3)|
|P2||Test Pattern (TESTPAT)||Forces the LVDS data outputs to be a test pattern. When TESTPAT is high digital outputs are a test pattern, and when TESTPAT is low digital outputs are the ADC conversion result.||TESTPAT = High (Pins 1 and 2) TESTPAT = Low (Pins 2 and 3)|
|P3||Lane Mode Selection||The ADC outputs two bits at a time on DA-/DA+ and DB-/DB+ when two-lane output mode is high, and the ADC outputs one bit at a time on DA-/DA+ and DB-/DB+ when two-lane output mode is low.||TWOLANES = High (Pins 1 and 2) TWOLANES = Low (Pins 2 and 3)|
|P4||FMC Connector (LPC)||Low pin count FMC connector used to connect the EVAL-CN0577-FMCZ hardware to various different FPGA development boards and kits.||N/A|
|J1||Positive Analog Input||This is the positive input to the EVAL-CN0577-FMCZ, which connects to external signal sources via an SMA connection.||0 to 4.096 V|
|J2||Negative Analog Input||This is the negative input to the EVAL-CN0577-FMCZ, which connects to external signal sources via an SMA connection.||0 to -4.096 V|
|J3||External Clock||If an external clocking source is desired in your system this is where you will need to connect it. Along with connecting it you will also need to update the solder jumper to change from the onboard crystal oscillator.|| On-board Crystal Oscillator (default 120MHz)
External source (120MHz desired)
Power to the EVAL-CN0577-FMCZ comes directly from the +12 V supply provided through the FMC connector.
The SMA connectors on the EVAL-CN0577-FMCZ (VIN+ and VIN−) provide analog inputs from a low noise, audio precision signal source (such as the Audio Precision audio analyzer).
The EVAL-CN0577-FMCZ clock diagram is shown in Figure 19. An on-board 120 MHz voltage controlled crystal oscillator is used to provide the clock for the EVAL-CN0577-FMCZ and the FPGA. This ultralow noise oscillator has a typical phase noise of -162 dBc/Hz at 10 kHz offset, a tuning voltage range of 0 V to 3.3 V, and a frequency pulling range of 28 ppm to 55 ppm. Additionally, this crystal oscillator has an RMS jitter of <50 fs to 100 fs at 100 MHz carrier.
The clock is fanned out to the retiming flip-flop and the FPGA. An ADG3241 level shifter converts the clock's 3.3 V logic level to the 2.5 V level required by the retiming flip-flop. An ADN4661 converts the 3.3 V clock to LVDS signaling, which is then forwarded to a global clock connection on the FMC connector.
If the EVAL-CN0577-FMCZ is to be synchronized to other circuits, or if tighter frequency accuracy or drift frequency drift is required, an external clock can be applied to the external clock connector. If the external clock frequency is significantly higher or lower than the on-board 120 MHz clock, reanalyze the entire circuit including the FPGA timing constraints.
The external clock circuitry also includes a high speed single inverter that provides AC coupling and balances the rise and fall times. This device has a typical time propagation delay of 2.4 ns and achieves a high output drive, while maintaining low static power dissipation over a broad VCC operating range.
The following is the list of items needed in order to replicate this demo.
If using ADALM2000 as input source:
For the device to run, the SD card should be loaded with Analog Devices Kuiper Linux, a distribution based on Raspbian from the Raspberry Pi Foundation. It incorporates Linux device drivers for ADI products as well as tools and other software products designed and created with ease of use in mind. The reasoning behind creating this distribution is to minimize the barriers to integrating ADI hardware devices into a Linux-based embedded system.
Access to the embedded system can be through a remote PC connected either via LAN cable or Wi-Fi.
In order to control the EVAL-CN0577-FMCZ, you will need to install ADI Kuiper Linux on an SD card. Complete instructions, including where to download the SD card image, how to write it to the SD card, and how to configure the system are provided at Kuiper Images. Write the image and follow the system configuration procedure.
To set up the complete system using Audio Precision audio analyzer as input source, follow these steps:
Using ADALM2000 as input source:
There are two main tools which a user has the option to interact with the EVAL-CN0577-FMCZ.
To be able to connect your device, the software must be able to create a context. The context creation in the software depends on the backend used to connect to the device as well as the platform where the EVAL-CN0577-FMCZ is attached. The platform currently supported for the CN0557: ZedBoard using the ADI Kuiper Linux. The user needs to supply a URI which will be used in the context creation. The Libiio is a library for interfacing with IIO devices.
Install the Libiio package on your machine.
The iio_info command is a part of the libIIO package that reports all IIO attributes.
Upon installation, simply enter the command on the terminal command line to access it.
Prompting this on the command terminal in your windows PC will give you the ip address to access the EVAL-CN0577-FMCZ.
A warning might appear if you have existing ECDSA host key for the ip address used. To get rid of the warning message, remove the content of the text file in C:\\Users\\<user_name>/.ssh/known_hosts. Otherwise, you will be prompted to check for the authenticity of the host and for confirmation to continue to connect with the ECDSA. Enter yes to proceed. Use analog when prompted with the password.
analog@analog:~$ iio_info -u ip:<ip_address>
There are different commands that can be used to manage the device being used. The iio_attr command reads and writes IIO attributes.
analog@analog:~$ iio_attr [OPTION]...
analog@analog:~$ iio_attr -a -C
Make sure to download/update to the latest version of IIO-Oscilloscope.
PyADI-IIO is a python abstraction module for ADI hardware with IIO drivers to make them easier to use. This module provides device-specific APIs built on top of the current libIIO python bindings. These interfaces try to match the driver naming as much as possible without the need to understand the complexities of libIIO and IIO.
After installing and configuring PYADI-IIO in your machine, you are now ready to run python script examples. In our case, run the ltc2387_example.py found in the examples folder.
.../pyadi-iio/examples $ python3 ltc2387_example.py
Github link for the python sample script: CN0577 Python Example
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