This version (11 Feb 2022 15:43) was approved by sergiu arpadi.The Previously approved version (14 Jan 2021 05:12) is available.
Table of Contents
CN0540 HDL Reference Design
Overview
The HDL reference design for the CN0540 provides all the interfaces that are necessary to interact with the devices on the 24-bit data acquisition system designed for IEPE sensors.
The design have a SPI Engine instance to control and acquire data from the AD7768-1 24-bit precisions ADC, providing support to capture continuous samples at maximum sampling rate. Currently the design support FPGA carriers from both Intel and Xilinx.
Used devices
Evaluation board
Supported FPGA carrier
HDL Design Description
The design is built upon ADI's generic HDL reference design framework. In the ADI Reference Designs HDL User Guide can be found an in-depth presentation and instructions about the HDL design framework in general.
The reference design uses the standard SPI Engine Framework to interface the AD7768-1 ADC. The SPI offload module, which can be used to capture continuous data stream at maximum data rate, is triggered by the DRDY (data ready) signal of the device.
In order to build the HDL design the user has to go through the following steps:
- Confirm that you have the right tools (see Release notes)
- Clone the HDL GitHub repository (see https://wiki.analog.com/resources/fpga/docs/git)
- Build the project (see https://wiki.analog.com/resources/fpga/docs/build)
HDL Downloads
Software sources
resources/eval/user-guides/circuits-from-the-lab/cn0540/hdl.txt · Last modified: 11 Feb 2022 15:43 by sergiu arpadi