This version (30 Jan 2021 23:14) was approved by Mihai Bancisor.The Previously approved version (28 Jan 2021 19:57) is available.
Table of Contents
ADRV936x SOM Revision History
This page contains revision details for the ADRV936x SOM boards.
ADRV9361-Z7035
Revision F
This is the current shipping version.
- Changes from Rev E to Rev F:
- The schematic did not change. We only made an adjustment to the layout.
- The RF traces were modified to improve the insertion loss and the return loss as well as the EVM.
- For some unknown reason the rev is “F2” not just “F”
Revision E
- Rev E Allegro Board File (This file is compressed). Get the Allegro FREE Physical Viewer (You need 16.6 or higher).
Revision D
- Changes from Rev C to Rev D:
- Moved all (4) GTX ports from Bank 111 to Bank 112 on the Zynq SoC in order to be in compliance with Xilinx recommended PCIe design rules. Functionally equivalent to Rev C.
- The GTX signal assignments at the JX micro headers were unchanged in order to maintain compatibility with existing carrier boards.
- Added revision and part number to the silkscreen and copper.
- The LED (D3), used to illuminate when PG_MODULE is asserted, now has its anode connected to the 3V3_I2C supply (formerly connected to 3.3V supply). This was done to allow the LED to be used as a visual state indicator during SOM power up, reflecting different states of the ADM1166 sequencer. In addition, the ADM1166 firmware was updated to include LED toggling (slow/fast), corresponding to specific power up states.
- Improved the power structure and increased the 0.95V current from 2A to 6A
- Added a 1000BASE-KX option for the Ethernet Phy (Ethernet Operation over Electrical Backplanes)
- Improved the layout to accommodate the power changes.
Revision C (First publicly available revision)
This is the first publicly available revision.
ADRV9364-Z7020 Hardware
Revision D
This is the current shipping version.
- Changes from Rev C to Rev D
- Improved the power structure and increased the 1V current from 2A to 4A
- Improved the layout to accommodate the power changes.
- Added a 1000BASE-KX option for the Ethernet Phy (Ethernet Operation over Electrical Backplanes)
- Improved the RF traces to have better insertion loss and return loss.
-
- There was a small typo in the rev D0 of the schematics (below), the net named
*_EN_AGC, was tied to theENABLEpin, and the net called*_ENABLEwas tied to theEN_AGCpin. This is fixed/updated in this schematic. copper/layout does not change, only the designation on the wire (for clarity).
-
- This has the notation error described above.
Revision C (First publicly available revision)
This is the first publicly available revision.
Support
Please refer to EngineerZone with questions on hardware/schematics/or using the ADRV936x RF SOMs.
resources/eval/user-guides/adrv9361-z7035/revision-history.txt · Last modified: 30 Jan 2021 23:10 by Mihai Bancisor