The DPD feature on the ADRV9029 transceiver enables users to offload power amplifier linearization tasks from the baseband processor to the transceiver. With DPD implemented on the transceiver, the user does not need to allocate JESD serializer/de-serializer resources for observing power amplifier feedback data through the ORx channels, resulting in significant system power savings. Interpolators leading to the DPD actuator allow the baseband processor to transmit data at a lower rate on the JESD204B/C link than is needed for the full DPD correction bandwidth. The lower data rate at JESD translates directly into power savings and less number of lanes. Integration of the DPD into the transceiver chip results in significant system level cost, space, and power savings when compared to conventional FPGA/ASIC based implementations.
The ADRV9029 transceiver provides digital signal processing capabilities in the embedded ARM processor using closed-loop feedback signals from the observation receiver channels. These functions improve transmitter performance, measure system output, and reduce system power consumption. The list of functions includes the following: digital pre-distortion (DPD), closed-loop gain control (CLGC) and crest factor reduction (CFR). These functions are collectively grouped together as the transceiver digital front end (DFE).
The figure below is a simplified system level overview of the transceiver signal chain with DFE processing blocks highlighted. There are five main DFE processing blocks: