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| resources:eval:user-guides:adrv9009-zu11eg:syncronization [15 Jun 2021 14:34] – [Clock tree synchronization considerations] Michael Hennerich | resources:eval:user-guides:adrv9009-zu11eg:syncronization [21 Feb 2024 09:06] (current) – [Reference distribution] Michael Hennerich |
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| A additional ''SYNC'' signals is used to generate the synchronization event. If the ''SYNC'' pin transitions from 0 to 1 with sufficient setup/hold margin with respect to the VCXO, this synchronization event is deterministically carried through PLL2, up the timing chain through the N2 divider, and then to the master SYSREF timer. This mechanism of deterministic phase adjustment allows synchronization of the SYSREF timer and output phases of multiple HMC7044 devices. Please see the datasheet chapter “**Multichip Synchronization via PLL2**" For further details. | A additional ''SYNC'' signals is used to generate the synchronization event. If the ''SYNC'' pin transitions from 0 to 1 with sufficient setup/hold margin with respect to the VCXO, this synchronization event is deterministically carried through PLL2, up the timing chain through the N2 divider, and then to the master SYSREF timer. This mechanism of deterministic phase adjustment allows synchronization of the SYSREF timer and output phases of multiple HMC7044 devices. Please see the datasheet chapter “**Multichip Synchronization via PLL2**" For further details. |
| |
| | ^ Function ^ File ^ |
| | | dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-jesd204-fsm-multisom-primary.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-jesd204-fsm-multisom-primary.dts]] | |
| | | dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-jesd204-fsm-multisom-secondary.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-jesd204-fsm-multisom-secondary.dts]] | |
| | | dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-primary.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-primary.dts]] | |
| | | dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-secondary.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-secondary.dts]] | |
| | |
| | <note warning> |
| | Depending on the Linux/Devicetree version, the HMC7044 eval board got replaced by [[resources:eval:user-guides:ad-synchrona14-ebz|AD-SYNCHRONA14-EBZ]] please see here: |
| | [[repo>linux/commit/ff537311d1fc7dc20d43a198b44007c22f2e9779]] |
| | |
| | <code> |
| | arch: arm64: adrv9009-zu11eg: Update hmc7044_ext |
| | To match default AD-SYNCHRONA14-EBZ configuration: |
| | |
| | CH8 - HMC7044 CLKOUT4 - CMOS |
| | CH10 - HMC7044 CLKOUT5 - LVPECL AC-COUPLED |
| | CH6 - HMC7044 CLKOUT6 - CMOS |
| | CH9 - HMC7044 CLKOUT12 - LVPECL AC-COUPLED |
| | </code> |
| | </note> |
| ==== Clock distribution ==== | ==== Clock distribution ==== |
| |
| This method is referred as **clock distribution**. All lower level clock-chips receive their input clock via ''FIN''/CLKIN1 and are synced via ''RFSYNC''/CLKIN0. | This method is referred as **clock distribution**. All lower level clock-chips receive their input clock via ''FIN''/CLKIN1 and are synced via ''RFSYNC''/CLKIN0. |
| |
| Depending on your [[resources:eval:user-guides:adrv9009-zu11eg:adrv2crr-fmc_carrier_board|ADRV2CRR-FMC]] Carrier Board Hardware revision following stuffing options need to be checked. | <note tip>This mode also allows for TRX baseband rates that would be otherwise not possible with the default installed VCXO of 122.880MHz. Let's say someone needs exactly 250.000MSPS. This becomes possible by providing a 500.000MHz or 1000.000MHz external clock.</note> |
| | |
| | Depending on your [[resources:eval:user-guides:adrv9009-zu11eg:adrv2crr-fmc_carrier_board|ADRV2CRR-FMC]] Carrier Board Hardware revision following stuffing options need to be checked. These are required to route ''RFSYNC'' DC coupled to the from SMA connectors J5 RFSYNC_P, J6 RFSYNC_N to the HMC7044 ''RFSYNC'' input. |
| | |
| | <note important>Rev C: |
| | * Replace C18, C19, C236, C240 with 0 Ohm resistors |
| | * Replace C289, C290 with 0 Ohm resistors |
| | * Unload 0 Ohm resistors from location R77, R112 and insert to R110, R111 |
| | Rev C.1: |
| | * Replace C289, C290 with 0 Ohm resistors |
| | * Unload 0 Ohm resistors from location R77, R112 and insert to R110, R111 |
| | </note> |
| |
| | C289 | bypass/short | | ^ Function ^ File ^ |
| | C290 | bypass/short | | | dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-primary-clockdist.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-primary-clockdist.dts]] | |
| | R110 | insert/short | | | dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-secondary-clockdist.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-secondary-clockdist.dts]] | |
| | R111 | insert/short | | |
| |
| ===== Hardware setup ===== | ===== Hardware setup ===== |
| ===== Software ===== | ===== Software ===== |
| |
| * 11/09/2020 | * [[:resources:tools-software:linux-software:kuiper-linux |Analog Devices Kuiper Linux]] |
| * {{ :resources:eval:user-guides:adrv9009-zu11eg:adrv9009_zu11eg_fmcomms8_nov9_2020.zip |ADRV9009-ZU11EG+FMCOMMMS8 Boot Files}} | |
| * 02/04/2021 | |
| * {{ :resources:eval:user-guides:adrv9009-zu11eg:adrv9009_zu11eg_feb4_2021.zip |ADRV9009-ZU11EG Boot Files}} | |
| * {{ :resources:eval:user-guides:adrv9009-zu11eg:adrv9009_zu11eg_fmcomms8_feb4_2021.zip |ADRV9009-ZU11EG+FMCOMMMS8 Boot Files}} | |
| |
| <note tip>The board which connects the external HMC7044 clockchip is refered as **primary** and requires the devicetree (system.dtb) from the primary folder in the archive. Likewise the board without the external clockchip connected is called **secondary**, and requires the devicetree from the secondary folder.</note> | <note tip>The board which connects the external HMC7044 clockchip is refered as **primary** and requires the devicetree (system.dtb) from the primary folder in the archive. Likewise the board without the external clockchip connected is called **secondary**, and requires the devicetree from the secondary folder.</note> |
| There are two domains of synchronization that are considered in this configuration, the ADRV9009 transceivers and the FPGAs. Synchronization for the transceivers is provided by the clocking tree of HMC7044s and the JESD protocol. In the diagram several HMC7044s are cascade from a parent, or what we call external HMC7044, who is responsible for general system reference (sysref) control. These reference signals feed the clock chips on the individual SOMs and FPGAs. | There are two domains of synchronization that are considered in this configuration, the ADRV9009 transceivers and the FPGAs. Synchronization for the transceivers is provided by the clocking tree of HMC7044s and the JESD protocol. In the diagram several HMC7044s are cascade from a parent, or what we call external HMC7044, who is responsible for general system reference (sysref) control. These reference signals feed the clock chips on the individual SOMs and FPGAs. |
| |
| {{ :resources:eval:user-guides:adrv9009_zu11eg:talise_clocking_tree.png?direct&400 |talise_clocking_tree}} | The System Clocking Tree Diagram is located here: |
| | {{ :resources:eval:user-guides:adrv9009-zu11eg:adrv9009_rfsom_clocking_tree.png?direct&400 |ADRV9009-ZU11EG Clock Tree}} |
| |
| During multi-chip synchronization (MCS), which is a feature of the ADRV9009s, all baseband data from the converters is synchronized across transceiver chips. This requires specific sysrefs to be captured at each of the transceiver simultaneously. This will also create deterministic phase differences between transceivers, when RFPLL sync is enabled, as well. The individual API rights to the transceivers, clock chips, and their sequences are detailed in the rx method of the python class [[https://github.com/analogdevicesinc/pyadi-iio/blob/master/adi/adrv9009_zu11eg_multi.py|adrv9009_zu11eg_multi.py]]. | During multi-chip synchronization (MCS), which is a feature of the ADRV9009s, all baseband data from the converters is synchronized across transceiver chips. This requires specific sysrefs to be captured at each of the transceiver simultaneously. This will also create deterministic phase differences between transceivers, when RFPLL sync is enabled, as well. The individual API rights to the transceivers, clock chips, and their sequences are detailed in the rx method of the python class [[https://github.com/analogdevicesinc/pyadi-iio/blob/master/adi/adrv9009_zu11eg_multi.py|adrv9009_zu11eg_multi.py]]. |
