The Quick Start Guides provide a simple step by step instruction on how to do an initial system setup for the ADRV9002NP/W1/PCBZ and ADRV9002NP/W2/PCBZ boards on various FPGA development boards. They will discuss how to program the bitstream, run a no-OS program or boot a Linux distribution.
The ADRV9002NP/W1/PCBZ and ADRV9002NP/W2/PCBZ is, by definition a “FPGA mezzanine card” (FMC), that means it needs a carrier to plug into. The carriers we support are:
|CMOS inteface||LVDS interface|
|ZC706||√ VADJ 1.8V¹||N/A²|
|Zed Board||√ VADJ 1.8V||N/A²|
|Arria 10 SoC||√||N/A³|
¹ Instruction for reprogramming the VADJ can be found here and here
² See Cmos only operation section
³ Not supported due sub-optimal mapping of the clock pins from the source synchronous interfaces.
On the ZC706 / ZedBoard platforms the FMC connectors map to HR IO banks. The HR banks have a limitation that when using LVDS I/O standard you must set the bank VCCO voltage to 2.5V, however the ADRV9001 evaluation board is using IO supplies of 1.8V and does not have level shifters for the single ended lines. Therefore the VCCO of the banks must be set to 1.8 V (VADJ) and limiting the operation to CMOS mode only. More information on the limitation see 7 Series Select IO guide section 'LVDS and LVDS_25' and Table 1-43
The supported OS are:
|Board||HDL||Linux Software||No-OS Software||Required Minimum Release|
|Arria 10 SoC||√||√||N/A||2020-R1|
In most carriers, the ADRV9002NP/W1/PCBZ and ADRV9002NP/W2/PCBZ boards connects to the HPC1 connector (unless otherwise noted). The carrier setup requires power, UART (115200), ethernet (Linux), DisplayPort or HDMI (if available) and/or JTAG (no-OS) connections. A few typical setups are shown below.
Evaluation boards were equipped with different silicon revisions. All boards built since the middle of December 2020 have C0 silicon, older ones use B0 silicon these are no longer shipped. You can identify the board you have based on its label.
Analog Devices will provide limited online support for anyone using the reference design with Analog Devices components via the EngineerZone.