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resources:eval:user-guides:adrv9002:axi_adrv9002 [24 Nov 2021 11:31] – [Parameters] Laszlo Nagyresources:eval:user-guides:adrv9002:axi_adrv9002 [01 Mar 2022 10:35] (current) – [Parameters] Laszlo Nagy
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 | TX_USE_BUFG  | 0 | Used in case of Xilinx 7 series devices; If set, will insert a global clock buffer on the Tx clock path. Useful if user logic does not fits in a clock region. | | TX_USE_BUFG  | 0 | Used in case of Xilinx 7 series devices; If set, will insert a global clock buffer on the Tx clock path. Useful if user logic does not fits in a clock region. |
 | USE_RX_CLK_FOR_TX | 0 | In case the received clock on the Tx source synchronous interface is not routed to clock capable pins, when setting this to 1 the Rx clock will be used to drive the Tx interface | | USE_RX_CLK_FOR_TX | 0 | In case the received clock on the Tx source synchronous interface is not routed to clock capable pins, when setting this to 1 the Rx clock will be used to drive the Tx interface |
 +| IODELAY_CTRL | 1 | IODELAY_CTRL parameter can have the values 0 or 1,  conditioning the instantiation of the IODELAY_CTRL primitive. You can place only one IODELAY_CTRL per I/O bank,   and need to set the same IO_DELAY_GROUP for the interfaces placed in that I/O bank. |
 | IO_DELAY_GROUP  | "dev_if_delay_group" | Used in case of Xilinx devices. Identifier of the IODELAYCTRL cell. | | IO_DELAY_GROUP  | "dev_if_delay_group" | Used in case of Xilinx devices. Identifier of the IODELAYCTRL cell. |
 | FPGA_TECHNOLOGY  | 0 | Auto populated by IPI. | | FPGA_TECHNOLOGY  | 0 | Auto populated by IPI. |
resources/eval/user-guides/adrv9002/axi_adrv9002.txt · Last modified: 01 Mar 2022 10:35 by Laszlo Nagy