This version is outdated by a newer approved version.
This version (17 Jan 2022 13:06) was approved by Mark Bolger.The Previously approved version (12 Jan 2022 11:24) is available.
This version (17 Jan 2022 13:06) was approved by Mark Bolger.The Previously approved version (12 Jan 2022 11:24) is available.This is an old revision of the document!
Table of Contents
==== PRELIMINARY ====
ADIN1300 and ADIN1200 Layout Considerations and Hardware Selection
The ADIN1300 and ADIN1200 need specific layout guidelines and hardware considerations for designing a physical layer device. This user guide will cover details on the ADIN1300 and ADIN1200 that include pin configuration, selection of components, layout recommendations, and other special guidelines that are unique to the ADIN1300 and ADIN1200 PHY’s. The sections within this user guide provide a high-level overview, and the document must be used in conjunction with the ADIN1200/1200 datasheets and additional apps notes found through the ADIN1200 and ADIN1300 product pages.
Pin Features and Hardware Selection
The pins of the ADIN1300 and ADIN1200 PHYs have certain details that are important for implementing a physical layer device. First, it is necessary to understand which power domain a specific pin belongs to. Second, some pins are shared for a bootstrapping feature and for a functional/PHY operation feature. These are described according to the pin group responsible for hardware configuration or bootstrapping, and the pin group responsible for general PHY function/operation. Take note that the bootstrapping pins are multi-function pins.
Hardware Configuration Pins/Bootstrapping Pins
The bootstrapping pins are responsible for the PHY’s initial configuration setting and features for its operation. Though the PHY can also be configured via software, this document only focuses on hardware configuration. More details on the hardware configuration pins are explained on the AN-2047 and AN-2043 Configuration Application Note.
PHY Configuration Pins
The PHY_CFG defines the speed, auto-negotiation, forced communications, Half duplex and full duplex communications, and other features like software power down and EEE. These pins have 4 level strapping resulting in 4 different modes per pin which can be seen in the datasheet. External resistors are required for proper bootstrapping on these pins as they have no internal resistors.
The PHY_CFG0 is under the AVDD3P3 domain and is shared with LED_0, and MAC Interface signal like COL/TX_ER. When LED is used, it is important to follow proper circuitry in strapping this pin, see datasheet. After bootstrap, when the MAC Interface selected is MII, this pin group defaults to COL. The PHY_CFG1 is under the VDDIO domain and is shared with the LINK_ST.
MAC Interface Selection Pins
The MACIF_SEL pins are the two pins responsible for the selection of MAC Interfaces during bootstrap. These pins have weak internal pull-down resistors that default the MAC_IF to RGMII when no external strapping is used. If no external strapping is used, it is important to check the host side pins to make sure the host is not pulling the MACIF_SEL pins to unexpected voltages during power up.
MACIF_SEL0 is shared with MAC Interface Clocking pins like RXC/RX_CLK. MACIF_SEL1 is shared with RX_CTL/RX_DV/CRS_DV pins.
The MAC Interface Selection can also be done using software configuration aside from the bootstrapping. However, when the selected MAC Interface is RMII, MAC interface selection is only possible using hardware configuration. Do not configure the MAC Interface to RMII using software.
Auto_MDIX Pin
The MDIX_MODE pin defines the MDI mode of the PHY either manual straight through, manual crossover or auto-MDI for a crossover on the other node, or side of the PHY communication. It follows the same mode selection of the PHY_CFG and does not have an internal pull-up or pull-down resistor so it is required for this pin to have external resistors. The MDIX_MODE pin is shared with other pin functions such as GP_CLK ad RX_ER. This pin is under the VDDIO domain.
PHY Address
The PHYAD_x pins are tied to VDDIO domain and has an internal pull-down resistors. Defaulting the device to PHY Address 0x0.
Functional Pins/Ethernet PHY Pins
The following list of pins are responsible for the Ethernet PHY operation and function. These pins have certain characteristics that must be understood when designing the physical layer device. Most of these pins are multi-function pins and used as bootstrapping pins also.
Media Dependent Interface Pins
The MDI pins are at 3.3V. MDI_x_x of both ADIN1200 and ADIN1300. All pins have individual impedances of 50Ω, or 100 Ω differential for layout impedances. These are voltage driven Ethernet MDI.
Management Interface Pins
The MDIO, MDC and INT_N (shared with CRS) are pins under the VDDIO domain. These pins are responsible for read/write functions of the PHY, accessing the PHY registers and subsystem. The INT_N is an active low, interrupt pin that requires an external pull-up resistor to VDDIO (1.5kΩ). MDIO also requires an external pull-up (1.5kΩ). MDC or management clock is capable up to 5.5MHz. The drive strength of these three pins is 8mA.
Clocking Interface
The clock interface of the ADIN1300 and ADIN1200 Ethernet PHY support a 25 MHz crystal. In situations where a host would control the clock of the PHY, a 25 MHz clock can be directly connected to CLK_IN. In ADIN1300, there is a 25Mhz clock oscillator at the CLK25_REF pin that can be used to drive another PHY via daisy chain. If this pin is not used, it is recommended to disable the pin thru software configuration. This is not present in ADIN1200. For RMII MAC interface, an external 50 MHz clock in the REF_CLK pin must be used.
Reset
The RESET_N pin is under the domain of AVDD3P3. The reset has a drive strength of 2 mA and does not have an internal pulldown or pullup resistor. It is recommended to pull this pin to AVDD3P3. However, there are applications where it is best to tie the reset pin to ground instead of 3.3V. For example, when the host side wants to drive the reset high for normal operation. This will hold the PHY in reset until the reset is cleared. As mentioned, RESET_N is under the domain of AVDD3P3 so for instances where the host uses an IO voltage of 1.8 V, for example, then a level shifter is required for the Reset of the ADIN1300 and ADIN1200 PHY.
Media Independent Interface
The MAC Interface Pins that includes the data transmit, data receive, delimiters, errors and clock are in the VDDIO domain.
LED Interface
LED_0 pin has a drive strength of 8 mA, is under the AVDD_3P3 domain, and is shared with PHY_CFG0 and other MAC interface pins (COL). This pin has a recommended LED circuitry described in the ADIN1300/ADIN1200 datasheet for proper operation.
Link Status
The LINK_ST pin is shared with a PHY Configuration pin. This pin has a 4mA driving strength. LINK_ST is not really intended to drive an LED directly. However, some applications require a 2nd LED. It is possible to use LINK_ST with proper buffer and taking into consideration the state of LINK_ST which is active high by default. This state is also configurable via software. This pin is under the VDDIO domain and is shared with PHY_CFG1.
Magnetics Selection
The most common way of isolating the PHY and RJ-45 is thru magnetic coupling. The transformer can either be a discrete transformer or integrated transformer, there are strengths and weaknesses to both.
1 - Ordered List Item. Discrete transformers occupy more space in the PCB, but it gives more freedom in terms of the layout of the MDI section. Also, discrete transformers are cheaper than integrated magnetics. Compared to their integrated counterpart discrete transformers can help improve EMC performance, decrease the likelihood of crosstalk and be less susceptible to losses and nonlinear distortion. Because of this, discrete transformers tend to offer better performance in a complete Ethernet system.
2 - Ordered List Item. The integrated transformer is a combined RJ45 connector jack with the magnetics built in. This provides a more compact solution due to fewer components, and in applications where space is at a premium, condenses the required footprint. Integrated transformers tend to be more expensive. Also, the cores are smaller and closer to each other, which can compromise EMC performance, increase the likelihood of crosstalk, and have impacts on performance by increasing losses and introducing nonlinear distortion.
3 - Ordered List Item. For optimum performance, a discrete transformer with an integrated common-mode choke is recommended for use with the ADIN1300 and ADIN1200 PHY. The common-mode choke is significant because it attenuates any common-mode signals picked up by the cable from the environment, improving the SNR of the system. Transformers with an autotransformer stage following the common-mode choke provide additional attenuation of common-mode noise. The ADIN1300 and ADIN1200 transmit drivers are voltage mode with on-chip terminations. Therefore, connect each of the center tap pins on the transformer on the ADIN1300 side separately to ground through a 0.1μF capacitor.
Layout Considerations
PCB Layout Considerations
This section is an overview of the key areas of interest during placement and layout of the PHY and corresponding support components. Take care when routing high speed interface signals to maximize signal performance and ensure optimum EMC performance, with a view to ensure critical signal traces are kept as short as possible to minimize noise coupling.
PHY Package Layout
The LFCSP has an exposed pad underneath the package that must be soldered to the PCB ground for mechanical and thermal reasons. For thermal impedance performance and to maximize heat removal, use of a 4 × 4 array of thermal vias beneath the exposed ground pad is recommended.
There are also two bus bars on either side of the exposed pad, these bus bars are connected to internal voltage rails and are not intended or required to be soldered to the board. The PCB land pattern must incorporate the exposed ground paddle with vias and two keep out areas around the bus bars in the footprint. No PCB traces or vias can be used in either of the keep out areas. The EVAL-ADIN1300FMCZ uses an array of 4 × 4 vias on a 0.75 mm grid arrangement, as shown below. The via pad diameter dimension is 0.02 in. (0.5015 mm) and the finished drill hole diameter is 0.01 in. (0.2489 mm).
Component Placement
Prioritization of the critical traces and components helps simplify the routing exercise. Place and orient the critical traces and components first to ensure an effective layout with minimal turns, vias, and crossing traces. For an Ethernet PHY layout, the important components are the crystal and load capacitors, the transformer on the MDI lines, and all bypass capacitors local to the device. Prioritize these components and the routing to them. Keep the PHY chip at least 1 in. away from the edge of the board. The following sections provide more detail for each of the areas.
MDI Lines
The MDI interface runs from the ADIN1300 PHY to the transformer, and from there to the RJ45 connector. Traces running from the MDI_x_x pins of the ADIN1300 to the magnetics must be on the same side of the board, kept as short as possible (ideally less than 1 inch in length), and individual trace impedance of these tracks kept below 50 Ω, with differential impedance of 100 Ω for each pair. The same recommendations apply for traces running from the magnetics to the RJ45 connector. Keep impedances constant throughout because any discontinuities may affect signal integrity.
Each pair must be routed together, trace widths kept the same throughout, trace lengths kept equal where possible, and avoid any right angles on these traces (use curves in traces or 45° angles). Avoid stubs on all signal traces. Where possible, route traces on the same layer. By taking these guidelines into account the difference in latency between each pair is minimized and this will also help in avoiding an increase in common mode noise.
Route traces over a continuous reference plane with no interruptions to reduce inductance.
Where possible, ensure a solid return path underneath all signal traces. Avoid routing signal traces across plane splits.
MAC Interface Pins
All signals within TX group should be length matched, similarly for all signals within RX group. Where possible route these interface pins on the same side as component pins. Keep trace lengths as short as possible. Route traces with an impedance of 50 Ω to ground.
The ADIN1300 has the capability to program the drive current of the RGMII pins to help minimize improve signal integrity and minimize ringing. Alternatively, series termination resistors can be placed in all RGMII output pins if further tuning is required.
Crystal Oscillator
To ensure minimum current consumption and to minimize stray capacitances, make connections between the crystal, capacitors, and ground as close to the ADIN1300 as possible and preferably on the same side as the ADIN1300 device. Caps should be tuned to adjust for pin capacitance and trace capacitance.
Power and Ground Planes
From a PCB layout point of view, it is important to place the decoupling capacitors as close as possible to the power and GND pins to minimize the inductance.
Magnetics Module Grounding
A split ground plane under the transformer minimizes noise coupling across the transformer and between adjacent coils within. Ensure a physical separation of the ground planes underneath the transformer. Make the width of this separation at least 100 mil.
RJ45 Module Grounding
For optimal EMC performance, it is recommended to use a metal shielded RJ45 connector with the shield connected to chassis ground. There must be an isolation gap between the chassis ground and the PHY IC ground with consistent isolation across all layers.
General Layout Considerations
There should be no right angles on PCB traces, either 45 degree turns or curved traces should be used
Avoid stubs on all signal traces
Keep PCB traces as short as possible
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resources/eval/user-guides/adin1300-and-adin1200/layout-considerations.1642421183.txt.gz · Last modified: 17 Jan 2022 13:06 by Mark Bolger