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resources:eval:user-guides:adin1300-and-adin1200:ksz8081_to_adin1200_phy_exchange_guide [17 Oct 2021 21:21] – cr Catherine Redmondresources:eval:user-guides:adin1300-and-adin1200:ksz8081_to_adin1200_phy_exchange_guide [17 Oct 2021 21:28] – cr Catherine Redmond
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 <WRAP group> <WRAP group>
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 ===== Hardware Configuration ===== ===== Hardware Configuration =====
  
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 +Strapping configurations are very specific to the device, consult the respective datasheets to determine the exact configuration for required use case. 
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 ==== RGMII ==== ==== RGMII ====
  
-The ADIN1200 also supports RGMII MAC interface mode. +The ADIN1200 also supports RGMII MAC interface mode.
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 The ADIN1200 has a Linux Driver available in the Linux mainline kernel. The ADIN1200 linux driver detail is captured here:  The ADIN1200 has a Linux Driver available in the Linux mainline kernel. The ADIN1200 linux driver detail is captured here: 
 https://wiki.analog.com/resources/tools-software/linux-drivers/net-phy/adin https://wiki.analog.com/resources/tools-software/linux-drivers/net-phy/adin
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 </WRAP> </WRAP>
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 +<note tip>The ADIN1200 has a Linux Driver available in the Linux mainline kernel.</note> 
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 The following example captures how to configure the ADIN1200 for an unmanaged configuration with RMII Interface, operating in Auto-negotiation mode advertising all speeds. The PHY will power up in this state, ready to establish a link with a link partner.  The following example captures how to configure the ADIN1200 for an unmanaged configuration with RMII Interface, operating in Auto-negotiation mode advertising all speeds. The PHY will power up in this state, ready to establish a link with a link partner. 
 The MAC interface configuration pins (MACIF_SEL0/1) are pulled to VDDIO, setting the PHY to RMII mode. GP_CLK is set to MODE_3 to configure an automatic MDIX operation. In addition, the PHY_CFG0 and PHY_CFG1 pins are configured for MODE_4 and MODE_1 respectively. The PHY_CFG0 pin is also shared with the LED_0 pin, it’s configuration with MODE_4 means an active low LED can be used on LED_0.  The MAC interface configuration pins (MACIF_SEL0/1) are pulled to VDDIO, setting the PHY to RMII mode. GP_CLK is set to MODE_3 to configure an automatic MDIX operation. In addition, the PHY_CFG0 and PHY_CFG1 pins are configured for MODE_4 and MODE_1 respectively. The PHY_CFG0 pin is also shared with the LED_0 pin, it’s configuration with MODE_4 means an active low LED can be used on LED_0. 
 +
 The following list summarizes an RMII auto negotiate, 10 Mbps or 100 Mbps full duplex or half duplex: The following list summarizes an RMII auto negotiate, 10 Mbps or 100 Mbps full duplex or half duplex:
   * MAC Interface = RMII    * MAC Interface = RMII 
resources/eval/user-guides/adin1300-and-adin1200/ksz8081_to_adin1200_phy_exchange_guide.txt · Last modified: 19 Jun 2023 17:33 by Mark Bolger