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resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_phy_exchange_guide [09 Nov 2021 18:51] – cr Catherine Redmondresources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_phy_exchange_guide [07 Jan 2022 15:23] – Formatting changed for even pages Mark Bolger
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 The ADIN1300 has compelling reasons for adoption versus this competitor PHY, such as reduced power consumption, lower latency, and smaller footprint due to the small package size.  The ADIN1300 has compelling reasons for adoption versus this competitor PHY, such as reduced power consumption, lower latency, and smaller footprint due to the small package size. 
  
-{{ :resources:eval:user-guides:adin1300-and-adin1200:dp83867_fig1.jpg?direct&600 |}}+{{:resources:eval:user-guides:adin1300-and-adin1200:figure1_motivators_to_migrate_dp83867.png|}}
  
 The ADIN1300 Ethernet PHY supports all the standard functions and pins of an Ethernet PHY and it is very straight forward to migrate an existing design to the ADIN1300.  The ADIN1300 Ethernet PHY supports all the standard functions and pins of an Ethernet PHY and it is very straight forward to migrate an existing design to the ADIN1300. 
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 Both devices require a minimum of 2 power supply rails, where the VDDIO is connected to the same power supply voltage as the MAC or as the PHY analog supply AVDD_3P3 (VDDA2P5). The VDDIO supply rail powers the MAC interface and MDIO blocks, this can operate from 1.8V, 2.5V or 3.3V. Both devices have an on-chip voltage regulator to generate the internal core supply rail. The supply requirements are listed in Table 1. Both devices require a minimum of 2 power supply rails, where the VDDIO is connected to the same power supply voltage as the MAC or as the PHY analog supply AVDD_3P3 (VDDA2P5). The VDDIO supply rail powers the MAC interface and MDIO blocks, this can operate from 1.8V, 2.5V or 3.3V. Both devices have an on-chip voltage regulator to generate the internal core supply rail. The supply requirements are listed in Table 1.
  
- +{{:resources:eval:user-guides:adin1300-and-adin1200:table1_overview_of_power_supply_rails_dp83867.png|}}
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table1.png?nolink&600|}}+
  
 The ADIN1300 is robust to power supply sequencing and the power can be applied in any order.  The ADIN1300 is robust to power supply sequencing and the power can be applied in any order. 
 Decoupling requirements for each device differ as described in Table 2 Decoupling requirements for each device differ as described in Table 2
  
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table2.png?nolink&600|}} +{{:resources:eval:user-guides:adin1300-and-adin1200:table2_decoupling_requirements_for_each_phy_dp83867.png|}}
  
  
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 An external resistor is required to bias internal reference circuitry for both DP83867 and ADIN1300. The ADIN1300 requires a 3.01 kΩ resistor (1% tolerance, 100 ppm/°C temperature coefficient) connected to pin 10.  The DP83687 uses an 11 kΩ (1%) on pin 12 in QFN package or pin 15 in QFP package.  An external resistor is required to bias internal reference circuitry for both DP83867 and ADIN1300. The ADIN1300 requires a 3.01 kΩ resistor (1% tolerance, 100 ppm/°C temperature coefficient) connected to pin 10.  The DP83687 uses an 11 kΩ (1%) on pin 12 in QFN package or pin 15 in QFP package. 
  
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table3.png?nolink&600|}}+{{:resources:eval:user-guides:adin1300-and-adin1200:table3_bias_resistor_values_dp83867.png|}}
  
 ==== Media Dependent Interface (MDI) ==== ==== Media Dependent Interface (MDI) ====
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 The recommended external circuit for the interface to the magnetics and RJ-45 is shown in Figure 2. The recommended external circuit for the interface to the magnetics and RJ-45 is shown in Figure 2.
  
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_fig2.png?nolink&600|}} 
 </WRAP> </WRAP>
  
 <WRAP half column> <WRAP half column>
  
 +{{:resources:eval:user-guides:adin1300-and-adin1200:figure2_isolating_using_discrete_magnetics_dp83867.png|}}
  
 ==== MDIO/Management Interface ==== ==== MDIO/Management Interface ====
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 The default LED operation is on if the Link is up and blinks when there is activity, this operation can be reprogrammed through MDIO write.  The default LED operation is on if the Link is up and blinks when there is activity, this operation can be reprogrammed through MDIO write. 
 For the LED_0 of the ADIN1300, it can be configured with 4-level strapping. The strapping configuration will have an impact on how the LED function operates and needs to be considered if the LED pins are used to directly drive an LED. If the strap pin is pulled high by the strapping resistors, (MODE_3/MODE_4) the output will be configured as an active low driver and conversely if the strapping input is pulled low (MODE_0/MODE_1), the output will be configured as active high. This LED circuit should be configured accordingly.  For the LED_0 of the ADIN1300, it can be configured with 4-level strapping. The strapping configuration will have an impact on how the LED function operates and needs to be considered if the LED pins are used to directly drive an LED. If the strap pin is pulled high by the strapping resistors, (MODE_3/MODE_4) the output will be configured as an active low driver and conversely if the strapping input is pulled low (MODE_0/MODE_1), the output will be configured as active high. This LED circuit should be configured accordingly. 
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_fig3.png?nolink&600|}}+ 
 +{{:resources:eval:user-guides:adin1300-and-adin1200:figure3_led0_hardware_config_dp83867.png|}}
  
 === Link Status, LINK_ST === === Link Status, LINK_ST ===
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 The RGMII interface is the communication path between the PHY and MAC devices. The RGMII interface has a low pin count interface supports 10M, 100M and Gigabit operation, with a total of 12 pins for data transmission, reception and to signal errors or collision. It is the most common interface for Gigabit applications and has the lowest latency.  Table 5 shows a pin overview of both devices for the RGMII MAC interface mode.  The RGMII interface is the communication path between the PHY and MAC devices. The RGMII interface has a low pin count interface supports 10M, 100M and Gigabit operation, with a total of 12 pins for data transmission, reception and to signal errors or collision. It is the most common interface for Gigabit applications and has the lowest latency.  Table 5 shows a pin overview of both devices for the RGMII MAC interface mode. 
 Both devices support the internal delay on the clocks. By default, the ADIN1300 is configured in RGMII mode with a 2 ns delay on RXC and TXC. Both devices support the internal delay on the clocks. By default, the ADIN1300 is configured in RGMII mode with a 2 ns delay on RXC and TXC.
-{{ :resources:eval:user-guides:adin1300-and-adin1200:rgmii_table4.jpg?direct&600 |}}+ 
 +{{:resources:eval:user-guides:adin1300-and-adin1200:table4_rgmii_mc_interface_pin_mode_comparison_dp83867.png|}} 
 === MII Interface === === MII Interface ===
  
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 The ADIN1300 sub-system registers provide user with ability to reconfigure which pin the COL and CRS functions are provided on (option of redirecting to GP_CLK, LINK_ST or INT_N). This requires a register write over MDIO interface to reconfigure.  The ADIN1300 sub-system registers provide user with ability to reconfigure which pin the COL and CRS functions are provided on (option of redirecting to GP_CLK, LINK_ST or INT_N). This requires a register write over MDIO interface to reconfigure. 
 Note, the DP83867IR only support MII mode with the 64-QFP 12x12 mm package. Note, the DP83867IR only support MII mode with the 64-QFP 12x12 mm package.
-{{ :resources:eval:user-guides:adin1300-and-adin1200:mii_table5.jpg?direct&600 |}}+ 
 +{{:resources:eval:user-guides:adin1300-and-adin1200:table5_mii_mac_interface_pin_mode_comparison_dp83867.png|}}
  
 === RMII Interface === === RMII Interface ===
  
 The DP83867 does not support the RMII interface. RMII is a reduced MII interface using fewer pins as shown in Table 6. The pin count for this interface is 8 pins.  The DP83867 does not support the RMII interface. RMII is a reduced MII interface using fewer pins as shown in Table 6. The pin count for this interface is 8 pins. 
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table6.png?nolink&600|}}+{{:resources:eval:user-guides:adin1300-and-adin1200:table6_rmii_mac_interface_pin_mode_comparison_dp83867.png|}}
 In RMII mode, the ADIN1300 requires an external 50MHz clock applied to XTAL_I. This clock could come from the MAC. In RMII mode, the ADIN1300 requires an external 50MHz clock applied to XTAL_I. This clock could come from the MAC.
- 
-==== Output Clocks ==== 
- 
-The ADIN1300 provides a 25 MHz output reference clock on the REF_CLK pin. This can be used a 25 MHz input reference clock for another PHY device.  
-The ADIN1300 can optionally provide a number of clock signals on the GP_CLK pin. This is configured via MDIO writes and the clocks available are a 125 MHz free running clock, 25 MHz clock and 25 MHz/125 MHz recovered clock.  
- 
- 
- 
  
  
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 <WRAP half column> <WRAP half column>
  
 +==== Output Clocks ====
 +
 +The ADIN1300 provides a 25 MHz output reference clock on the REF_CLK pin. This can be used a 25 MHz input reference clock for another PHY device. 
 +The ADIN1300 can optionally provide a number of clock signals on the GP_CLK pin. This is configured via MDIO writes and the clocks available are a 125 MHz free running clock, 25 MHz clock and 25 MHz/125 MHz recovered clock. 
  
 ===== Hardware Configuration ===== ===== Hardware Configuration =====
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 When configuring any strapping configurations, ensure to review the default state of the MAC side, whether the pins are being driven when coming out of reset or if there are internal pulls. Understanding the behavior on the MAC side is key to ensuring there are no conflicts with the hardware strapping implemented, or to adjust the strapping resistor values if required.  When configuring any strapping configurations, ensure to review the default state of the MAC side, whether the pins are being driven when coming out of reset or if there are internal pulls. Understanding the behavior on the MAC side is key to ensuring there are no conflicts with the hardware strapping implemented, or to adjust the strapping resistor values if required. 
 The DP83867 uses 4-level strapping options throughout, while the ADIN1300 uses a mix of 2-level and 4-level. In general, strapping pins are multi-functional and have different operation after the device is brought out of reset. The ADIN1300 has internal pull downs on many of its strapping pins (not all), therefore it would be possible to minimize external strapping resistors. The DP83867 uses 4-level strapping options throughout, while the ADIN1300 uses a mix of 2-level and 4-level. In general, strapping pins are multi-functional and have different operation after the device is brought out of reset. The ADIN1300 has internal pull downs on many of its strapping pins (not all), therefore it would be possible to minimize external strapping resistors.
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_fig4.png?nolink&600|}} + 
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table7.png?nolink&600|}}+{{:resources:eval:user-guides:adin1300-and-adin1200:figure4_adin1300_hardware_strapping_2and4_level_dp83867.png|}} 
 + 
 +{{:resources:eval:user-guides:adin1300-and-adin1200:table7_4level_strapping_resistor_ratios_adin_1300_dp83867.png|}} 
 Strapping configurations are very specific to the device, consult the respective datasheets to determine the exact configuration for required use case.  Strapping configurations are very specific to the device, consult the respective datasheets to determine the exact configuration for required use case. 
 The DP83867 has internal 9 kΩ pulldown resistors on all pins used for strapping functions. The DP83867 has internal 9 kΩ pulldown resistors on all pins used for strapping functions.
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table8.png?nolink&600|}}+ 
 +{{:resources:eval:user-guides:adin1300-and-adin1200:table8_4level_strapping_resistor_ratios_dp83867.png|}} 
 ==== Hardware Configuration of Speed ==== ==== Hardware Configuration of Speed ====
    
 For the ADIN1300, speed configuration is done using two pins, PHY_CFG0 and PHY_CFG1. These pins do not have any internal pull resistors, therefore external strapping is required. Both pins support 4-level strapping, providing much flexibility in terms of the possible combinations, such as Auto-neg speeds shown in Table 9 or Forced modes shown in Table 10. Review the datasheet hardware configuration pin section for full detail on the possible settings using these pins.  For the ADIN1300, speed configuration is done using two pins, PHY_CFG0 and PHY_CFG1. These pins do not have any internal pull resistors, therefore external strapping is required. Both pins support 4-level strapping, providing much flexibility in terms of the possible combinations, such as Auto-neg speeds shown in Table 9 or Forced modes shown in Table 10. Review the datasheet hardware configuration pin section for full detail on the possible settings using these pins. 
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table910.png?nolink&600|}}+
 </WRAP> </WRAP>
  
 <WRAP half column> <WRAP half column>
 +
 +{{:resources:eval:user-guides:adin1300-and-adin1200:table9_autoneg_speeds_1300_dp83867.png|}}
 +{{:resources:eval:user-guides:adin1300-and-adin1200:table10_forced_neg_speeds_1300_dp83867.png|}}
  
 ==== Hardware Configuration of Auto-MDIX ==== ==== Hardware Configuration of Auto-MDIX ====
    
 Selection of Auto-MDIX for the ADIN1300 is done using one pin, (MDIX_MODE) with 4-level strapping.  Selection of Auto-MDIX for the ADIN1300 is done using one pin, (MDIX_MODE) with 4-level strapping. 
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table11.png?nolink&600|}}+ 
 +{{:resources:eval:user-guides:adin1300-and-adin1200:table11_auto_mdix_modes_1300_dp83867.png|}} 
 ==== MAC Interface Selection ==== ==== MAC Interface Selection ====
  
 The ADIN1300 uses two hardware pins, MACIF_SEL0 and MACIF_SEL1 to provide user ability to select different MAC interfaces. These two pins have internal weak pull downs, therefore the default operation would be RGMII with delays as shown in Table 12. To configure any other MAC interface mode, use 10kΩ pull up or pull down resistors to select accordingly.   The ADIN1300 uses two hardware pins, MACIF_SEL0 and MACIF_SEL1 to provide user ability to select different MAC interfaces. These two pins have internal weak pull downs, therefore the default operation would be RGMII with delays as shown in Table 12. To configure any other MAC interface mode, use 10kΩ pull up or pull down resistors to select accordingly.  
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table12.png?nolink&600|}}+{{:resources:eval:user-guides:adin1300-and-adin1200:table12_mac_interface_selection_1300_dp83867.png|}}
  
 ==== Hardware Configuration of PHY Address ==== ==== Hardware Configuration of PHY Address ====
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 The ADIN1300 is available in a 40 lead LFCSP (6 mm x 6 mm footprint). The DP83867 is available in two package options, 48 lead QFN (7 mm x 7 mm) and 64 pin QFP (12 mm x 12 mm). Due to the smaller package footprint and differing pinout, the ADIN1300 is not a drop-in replacement for the DP83867 product. It will require a re-spin of schematic and board layout to achieve this exchange.  The ADIN1300 is available in a 40 lead LFCSP (6 mm x 6 mm footprint). The DP83867 is available in two package options, 48 lead QFN (7 mm x 7 mm) and 64 pin QFP (12 mm x 12 mm). Due to the smaller package footprint and differing pinout, the ADIN1300 is not a drop-in replacement for the DP83867 product. It will require a re-spin of schematic and board layout to achieve this exchange. 
  
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table13.png?nolink&400|}}+{{:resources:eval:user-guides:adin1300-and-adin1200:table13_package_comparrison_dp83867.png|}}
  
 The DP83867 requires the 64-QFP (12 mm x 12 mm) option to support MII or RMII interface. The DP83867 requires the 64-QFP (12 mm x 12 mm) option to support MII or RMII interface.
  
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_table14.png?nolink&400|}}+{{:resources:eval:user-guides:adin1300-and-adin1200:table14_package_comparrison_dp83867.png|}}
  
 The underside of the LFCSP package for the ADIN1300 includes an exposed paddle which should be soldered directly to the board with an array of vias for thermal purposes. There are also two exposed stripes adjacent to the exposed paddle. These do not need to be soldered to the board, they should be treated as a keep out area as they are connected to supply rails in the device, therefore should not be tied to ground and there should be no routing or traces on the PCB layer directly underneath them.  The underside of the LFCSP package for the ADIN1300 includes an exposed paddle which should be soldered directly to the board with an array of vias for thermal purposes. There are also two exposed stripes adjacent to the exposed paddle. These do not need to be soldered to the board, they should be treated as a keep out area as they are connected to supply rails in the device, therefore should not be tied to ground and there should be no routing or traces on the PCB layer directly underneath them. 
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 Both devices include integrated termination resistors on the MDI paths. These are voltage mode PHYs, no external resistors are required for biasing and no supply voltage is required at the center tap of the transformer.  Both devices include integrated termination resistors on the MDI paths. These are voltage mode PHYs, no external resistors are required for biasing and no supply voltage is required at the center tap of the transformer. 
 +
 +</WRAP>
 +
 +<WRAP half column>
 +
 ==== RGMII Drive/Termination resistors ==== ==== RGMII Drive/Termination resistors ====
  
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 ==== GMII ==== ==== GMII ====
 The DP83867 supports GMII interface in the 64-lead QFP (12 mm x 12 mm) package option. The ADIN1300 does not support GMII interface. The DP83867 supports GMII interface in the 64-lead QFP (12 mm x 12 mm) package option. The ADIN1300 does not support GMII interface.
-</WRAP> 
- 
-<WRAP half column> 
  
 ===== Software Considerations ===== ===== Software Considerations =====
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 The following is a side-by-side comparison of the package and pinouts, showing the position of the corresponding functional pins on each device The following is a side-by-side comparison of the package and pinouts, showing the position of the corresponding functional pins on each device
-{{ :resources:eval:user-guides:adin1300-and-adin1200:fig5.jpg?direct&600 |}}+{{:resources:eval:user-guides:adin1300-and-adin1200:figure5_pinout_comparison_dp83867.png|}}
 ---- ----
 ===== Feature Comparison Table ===== ===== Feature Comparison Table =====
-{{ :resources:eval:user-guides:adin1300-and-adin1200:table15.jpg?direct |}}+{{:resources:eval:user-guides:adin1300-and-adin1200:table15_feature_comparrison_table_dp83867.png|}}
 ===== Example Configuration for RGMII ===== ===== Example Configuration for RGMII =====
  
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     *PHY_CFG1 = MODE_1 = 10 kΩ pull-down resistor      *PHY_CFG1 = MODE_1 = 10 kΩ pull-down resistor 
  
-{{:resources:eval:user-guides:adin1300-and-adin1200:dp83867_to_adin1300_fig6.png?nolink|}}+{{:resources:eval:user-guides:adin1300-and-adin1200:figure6_rmii_auto_neg_allspeeds_half_or_full_duplex_dp83867.png|}}
resources/eval/user-guides/adin1300-and-adin1200/dp83867_to_adin1300_phy_exchange_guide.txt · Last modified: 19 Jun 2023 17:35 by Mark Bolger

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