The purpose of this application note is to describe the configuration of the ADIN1300 for the various Ethernet PHY compliance test modes as set out by IEEE802.3.
The ADIN1300 supports the IEEE test modes, Test Mode 1, Test Mode 2, Test Mode 3 and Test Mode 4 used for 1000BASE-T IEEE compliance testing. The ADIN1300 has some additional test modes that are useful for 10BASE-T and 100BASE-TX compliance testing. Details of the registers, sequences of writes are captured in this document. Use this application note in conjunction with the product datasheet.
When performing this testing, user will need Ethernet compliance test fixture and associated Ethernet physical layer compliance software. There are a number of vendors provide Ethernet Compliance test equipment. For ADI in-house validation, we used Tektronix TDSET3 compliance software in addition to having UNH (University of New Hampshire perform compliance testing).
Once equipment is in place and hardware powered and connected to the test fixture, configure the PHY through the MDIO interface to set the required test mode and use the compliance software to record and report the results.
To ensure the device is in a known state, either start from a power cycle or alternatively, issue the following writes to reset the device with fresh read of the hardware configuration.
The ADIN1300 supports a range of extended management interface registers which can be accessed using Clause 45 access or alternatively using Clause 22 access through the EXT_REG_PTR (address 0x0010) and EXT_REG_DATA (address 0x0011), these registers provide user ability to read/write to the extended register space (any register greater than 0x001F) indirectly. If using Clause 22 access, write the 16-bit register address into the EXT_REG_PTR register and then read or write the EXT_REG_DATA register.
The ADIN1300 supports the IEEE test modes, Test Mode 1, Test Mode 2, Test Mode 3 and Test Mode 4 used for 1000BASE-T IEEE compliance testing. An IEEE test mode can be selected by writing to register address 9, bits 15:13. The TST_MODE bit field can be used to select the transmit test waveforms required for Gigabit IEEE compliance testing.
Address: 0x09: Reset, 0x0200, Name: MSTR_SLV_CONTROL This address corresponds to the MASTER-SLAVE Control register specified in clause 22.214.171.124 of IEEE Std 802.3. Only Test mode bits are show in table below, refer to datasheet register map for further detail.
This test mode is used for a number of tests as follows:
To configure the device in Test Mode 1, issue the following writes over MDIO
This test mode is used to ensure the TX_TCLK jitter with respect to an un-jittered reference is within range. Note the ADIN1300 does not expose TX_TCLK directly. To configure the device in Test Mode 2, issue the following writes over MDIO
To configure the device in Test Mode 3, issue the following writes over MDIO
This test mode is used
To configure the device in Test Mode 4, issue the following writes over MDIO
For 100BASE-TX operation there are a variety of tests. There are two main test modes main register involved here is the B_100_TX_TST_MODE register at address 0xB413 (available via Clause 45 access)
Address: 0xB413, Reset: 0x0000, Name: B_100_TX_TST_MODE This register provides the ability to transmit a 100BASE-TX test signal.
To configure the device for 100BASE-TX VOD measurements, issue the following writes over MDIO
When operating in 10 Mbps speeds, the PHY is configured for 10BASE-Te transmit levels by default. 10BASE-T provides larger transmit levels and can be configured by clearing the B_10_E_EN register. The 10BASE-Te/T compliance tests are:
The B_10_TX_TST_MODE register is used to select transmit test signals useful for 10BASE-T compliance testing.
Address: 0xB412, Reset: 0x0000, Name: B_10_TX_TST_MODE This register provides the ability to transmit a 10BASE-T test signal.
To configure the device for 10BASE-T transmit test mode, consisting of 5MHz square wave on desired dimension, issue the following writes over MDIO
An alternative configuration, where the device is configured in 10BASE-T forced mode in loopback with Tx suppression disabled, with transmission of frames with random payloads using the frame generator as follows:
Setup for 10BASE-T forced mode in loopback with Tx suppression disabled, with transmission of frames with random payloads using the frame generator, configure as follows in sequence above
10BASE-T is configured by writing the following register – include it in the sequence above if 10BASE-T operation is required.