This guide provides some quick instructions on how to setup the AD9656 on the ZCU102 carrier board.
Clone NO-OS with the
git clone --recursive https://github.com/analogdevicesinc/no-OS
If however you've already cloned NO-OS without the
--recursive flag, you may initialize all the submodules in an existing NO-OS clone with:
git submodule update --recursive --init
Prior to building a no-OS project, it is required to set up some environment variables so that the build process may find the necessary tools (compiler, linker, SDK etc.).
Use the following commands to prepare your environment for building no-OS projects:
Go in the project directory that should be built.
The build process creates a build directory in the project folder:
build ├── app ├── bsp ├── obj ├── release.elf └── tmp
.hex file has been generated, make sure the board is powered on, JTAG cable connected and use the following commands to upload the program to the board or debug.
Uploading the binary to target is generically achieved with:
$ make run
Use the following command to launch the SDK associated to the used platform in order to be able to debug graphically by clicking the debug button:
$ make sdkopen
Fore more details about the available make rules, check out this page.
This guide provides some quick instructions on how to build and run the no-OS on almost all of the supported platforms.
Be sure you are using the latest release version and you have the corresponding branches for both HDL and no-OS(Release notes).
ADI does not distribute the bit/elf files of these projects. They must be built from the sources. The HDL User Guide provides detailed information and steps to build the HDL project on your desired carrier. The build flow is developed around GNU make. You may use a Windows or Linux OS, but do NOT seek OS- specific support. The prerequisite to the building process is that you are able to run 'quartus', 'vivado' and 'make' all from a shell (Cygwin or Linux).
Building the HDL is as simple as running make on your desired project and carrier.
hdl/projects/daq3/kcu105> make hdl/projects/daq3/zc706> make
hdl/projects/daq3/a10gx> make MMU=0
We strongly recommend having a clone of no-Os and HDL in the same folder:
In every project folder, you can find a separate subfolder for each supported carrier. In each carrier folder, there is a Makefile which points to the bit files and HDL deliverables (system_top.hdf/project_name.sof) and other makefiles (*.mk) containing the software dependencies.
Change your current directory to your targeted project and run make:
[~] cd fmcdaq2/zc706 [~] make
See Troubleshooting section for guideline how to solve make related issues.
Make sure that the FPGA is powered on and connected to the PC and then run the command:
[~] make run
The make run will downloads the bitstream on the FPGA and after that program the board with the elf file.
The software is started before the memory debugger disconnects.
After the software has been run on the FPGA, run the command:
[~] make capture
By default, the software captures (in case of ADC based projects) the data received from the device in the RAM.
rx_xfer.start_address = *_MEM_BASEADDR + OFFSET; rx_xfer.no_of_samples = value; dmac_start_transaction(ad_core_dma);
These values differ depending on the architecture and device.
The Makefiles have these parameters initialized with default values:
The number of samples is specified in the project's common Makefile. (ex: fmcadc4)
For example, for fmcomms2(AD9361: 2RF channels):
[~] make clean
make: *** No rule to make target `../../../hdl/projects/daq2/vc707/daq2_vc707.sdk/system_top.hdf', needed by `hw/system_top.bit'. Stop.
The HDL deliverables cannot be found. Maybe the targeted HDL project is not built, or the defined path is not valid. Make sure, that you build the HDL before running the no-OS or specify the location of the HDL deliverables explicitly.
[~] make HARDWARE=/<path_to_hdf>/system_top.hdf
[~] make M_SOPCINFO_FILE=/<path_to_sopcinfo>/system_bd.sopcinfo
The best place to start in the no-OS main function in “project/project_name.c”. It shows how individual components of a data path chain are initialized and programmed for the application. After you have the default setup working, feel free to add your own customization routines and/or signal processing functions to either HDL or no-OS.
//#define XILINX #define ALTERA