This is an old revision of the document!
The ADCs are set to run at full bandwidth mode 3 GSPS, which translates to a lane rate of 15.5 Gbps. Each converter has its own SYSREF that is driven from a common clock chip HMC7044. Ideally these SYREF lines should be length matched, if not the HMC has capability to adjust delays on its outputs. Sampling clocks are generated by the same HMC clock chip and should be ideally length matched as well.
Before building the hdl project setup your computer based on the following guide: Building HDL projects
git clone https://github.com/analogdevicesinc/hdl.git git checkout hdl_2019_r2; // or latest release cd hdl/projects/ad9208_dual_ebz/vcu118 make
Instructions on how to build the MicroBlaze Linux kernel and devicetrees from source can be found here:
First we need to prepare a working directory where we will gather all the required binary files.
From the HDL build directory locate the system_top.bit and copy it to the working directory. From the Linux build directory locate the simpleImage and copy it to the working directory.
mkdir <working_dir> cp <hdl_repo_dir>/projects/ad9208_dual_ebz_vcu118.runs/impl_1/system_top.bit <working_dir> cp <linux_repo_dir>/arch/microblaze/boot/simpleImage.vcu118_dual_ad9208 <working_dir>
Next step is to program the board with xsct or similar tool. See generic instructions for programming the MicroBlaze bases systems here Boot Kernel on FPGA Microblaze
xsct% connect xsct% fpga -f system_top.bit xsct% after 1000 xsct% target 3 xsct% dow simpleImage.vcu118_dual_ad9208.strip xsct% after 1000 xsct% con xsct% disconnect
The following devices should be present:
This specifies any shell prompt running on the target
# iio_info | grep iio:device iio:device0: hmc7044 iio:device1: axi-ad9208-0-hpc (buffer capable) iio:device2: axi-ad9208-1-hpc
From the UART console find out the board IP address that was allocated by the DHCP server. If you do not use a DHCP server manually assign an IP to the board Ethernet port.
When the device is configured from device tree into subclass 0 we can observe the two links are not synchronized and the channels present phase differences.
When the devices are configured into subclass 1 (default), we can observe the JESD links are synchronized and there is no phase difference between the input channels.
Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the EngineerZone.