Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
resources:eval:user-guides:ad9208_dual_ebz:ad9208_dual_ebz_hdl [10 May 2019 10:55] – [Block Diagram] Laszlo Nagyresources:eval:user-guides:ad9208_dual_ebz:ad9208_dual_ebz_hdl [26 Apr 2021 16:38] (current) – [More Information] Laszlo Nagy
Line 4: Line 4:
 ==== Functional Overview ==== ==== Functional Overview ====
 The AD9208-DUAL-EBZ reference design is a processor based (e.g. Microblaze) embedded system. The device interfaces to the FPGA transceivers followed by the individual JESD204B and ADC cores. The cores are programmable through an AXI-Lite interface. The samples are passed to the system memory (DDR).  The AD9208-DUAL-EBZ reference design is a processor based (e.g. Microblaze) embedded system. The device interfaces to the FPGA transceivers followed by the individual JESD204B and ADC cores. The cores are programmable through an AXI-Lite interface. The samples are passed to the system memory (DDR). 
 +
 +<WRAP center round download>
 +https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9208_dual_ebz
 +</WRAP>
 +
  
 The reference design supports the following evaluation board: The reference design supports the following evaluation board:
  
 ^Hardware ^Evaluation Document ^ ^Hardware ^Evaluation Document ^
-|[[adi>dual-AD9208|DUAL-AD9208]] | [[:resources:eval:ad9208-dual-ebz|DUAL-AD9208]] |+|[[adi>AD9208|DUAL-AD9208]] | DUAL-AD9208 |
  
  
Line 14: Line 19:
  
   * [[xilinx>VCU118]] FMC+ Slot   * [[xilinx>VCU118]] FMC+ Slot
 +
 +==== Building the HDL project ====
 +General build instructions can be found here: [[resources:fpga:docs:build|Building HDL]]
  
 ==== Block Diagram ==== ==== Block Diagram ====
-The data path and clock domains are depicted on the below diagram.+The data path and clock domains are depicted on the below diagram:
 {{ :resources:eval:user-guides:ad9208_dual_ebz:vcu118_ad9208_dual_ebz.png?nolink |}} {{ :resources:eval:user-guides:ad9208_dual_ebz:vcu118_ad9208_dual_ebz.png?nolink |}}
  
Line 23: Line 31:
 The links operate in Subclass 1 by using the SYSREF signal to edge align the internal local multiframe clock and to release the received data in the same moment from all lanes. Therefore ensuring that data from all channels is synchronized at the application layer. The links operate in Subclass 1 by using the SYSREF signal to edge align the internal local multiframe clock and to release the received data in the same moment from all lanes. Therefore ensuring that data from all channels is synchronized at the application layer.
  
-Both links operate with the following parameters: +Both links are set for full bandwidth mode and operate with the following parameters: 
   * Deframer paramaters: L=8, M=2, F=1, S=2, N’=16   * Deframer paramaters: L=8, M=2, F=1, S=2, N’=16
   * GLBLCLK – 375MHz (Lane Rate/40)   * GLBLCLK – 375MHz (Lane Rate/40)
   * REFCLK – 750MHz (Lane Rate/20)   * REFCLK – 750MHz (Lane Rate/20)
-  * SYSREF – 1.46MHz (DEVCLK/2048) +  * SYSREF – 1.46MHz (DEVCLK/2048) 
 +  * DEVCLK – 3000MHz 
   * JESD204B Lane Rate – 15Gbps   * JESD204B Lane Rate – 15Gbps
  
-Both transport layer components present on their output 256 bits at once, representing 16 samples per link or 8 samples per channel.  +Both transport layer components present on their output 256 bits at once on every clock cycle, representing 8 samples per converter. 
- +The two receive chains are merged together and transferred to the DDR with a single DMA. 
-The two channels from each converter are merged together and transferred to the DDR with a single DMA. +An ADC buffer is used to store 65k samples per converter in the fabric before transferring it with the DMA.
-An ADC buffer is used to store 65k samples per channel in the fabric before transferring it with the DMA.+
  
 === Clock sources === === Clock sources ===
 +The clock sources are depicted on the below diagram:
 +
 {{ :resources:eval:user-guides:ad9208_dual_ebz:ad9208_vcu118_clocking.png?nolink |}} {{ :resources:eval:user-guides:ad9208_dual_ebz:ad9208_vcu118_clocking.png?nolink |}}
  
-The global clock (LaneRate/40) it is received directly from the clockchip SCLKOUT9 output through the REFCLK1.+Both physical layer transceiver modules receive the same reference clock from the clock chip SCLKOUT8 output. 
 +The global clock (LaneRate/40) it is received directly from the clock chip SCLKOUT9 output. 
 + 
  
  
 +==== More Information ====
 +  * [[:resources:eval:user-guides:ad9208_dual_ebz:quickstart:vcu118 | AD9208-DUAL-EBZ Virtex UltraScale+ VCU118 Quick Start Guide]]
 +  * [[:resources:fpga:docs:hdl|ADI Reference Designs HDL User Guide]]
 +  * [[:resources:fpga:docs:hdl:generic_jesd_bds|Generic JESD204B block designs]]
 +  * [[:resources:fpga:peripherals:jesd204|JESD204B High-Speed Serial Interface Support]]
 +  * [[:resources:tools-software:linux-drivers:iio-adc:ad9208|AD9208 ADC Linux Driver]]
  
  
 ==== Support ==== ==== Support ====
-Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[https://ez.analog.com/community/fpga|EngineerZone]].+Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[ez>community/fpga|EngineerZone]].
resources/eval/user-guides/ad9208_dual_ebz/ad9208_dual_ebz_hdl.1557478511.txt.gz · Last modified: 10 May 2019 10:55 by Laszlo Nagy

Page Tools