Wiki

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision
Previous revision
resources:eval:user-guides:ad9083:ad9083_evb_reference_hdl [26 Mar 2021 18:07] – [Support] sergiu arpadiresources:eval:user-guides:ad9083:ad9083_evb_reference_hdl [17 Nov 2022 15:24] (current) – Add required hardware section Liviu-Mihai Iacob
Line 22: Line 22:
  
   * [[xilinx>ZCU102]] - HPC0 Slot   * [[xilinx>ZCU102]] - HPC0 Slot
 +  * [[https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html|A10SOC]] - FMC A (J29)
  
-==== Block Diagram ====+===== Required Hardware =====
  
-The data path and clock domains are depicted on the below diagram:+  * [[adi>AD9083|AD9083]] 
 +  * [[xilinx>ZCU102]] / [[https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html|A10SOC]] 
 +  * FMC extender (for A10SOC setup)
  
-{{:resources:fpga:docs:AD9083_evb_2.svg?800|}}+==== Block Diagram ====
  
-The design has one JESD receive chain with 4 lanes at rate of 10Gbps. The JESD receive chain consists of a physical layer represented by an XCVR modulelink layer represented by an RX JESD LINK module and transport layer represented by a RX JESD TPL module. The links operate in Subclass 0 since it is not using the SYSREF signal. +For both platformsthe link is set for full bandwidth mode and operate with the following parameters:
- +
-Both links are set for full bandwidth mode and operate with the following parameters:+
  
 Deframer paramaters: L=4, M=16, F=8, S=1, N’=16 Deframer paramaters: L=4, M=16, F=8, S=1, N’=16
Line 42: Line 43:
  
 Beacause of the F=8 parameter the JESD Link IP will have different input and output frequencies and bus widths. Data will enter the IP on 4 32bit wide channels (128b) at 250MHz (link clock) and will exit on a 256bit interface clocked at 125MHz (device clock). The transport layer component presents on its output 256 bits at once on every clock cycle, representing 1 sample per converter. The receive chain is then transferred to the DDR using a DMA. Beacause of the F=8 parameter the JESD Link IP will have different input and output frequencies and bus widths. Data will enter the IP on 4 32bit wide channels (128b) at 250MHz (link clock) and will exit on a 256bit interface clocked at 125MHz (device clock). The transport layer component presents on its output 256 bits at once on every clock cycle, representing 1 sample per converter. The receive chain is then transferred to the DDR using a DMA.
 +
 +The data path and clock domains are depicted on the below diagram:
 +
 +=== Xilinx ===
 +
 +{{:resources:fpga:docs:AD9083_evb_2.svg?800|}}
 +
 +The design has one JESD receive chain with 4 lanes at rate of 10Gbps. The JESD receive chain consists of a physical layer represented by an XCVR module, a link layer represented by an RX JESD LINK module and transport layer represented by a RX JESD TPL module. The links operate in Subclass 0 since it is not using the SYSREF signal.
 +
 +=== Intel ===
 +
 +{{:resources:eval:user-guides:ad9083_evb_a10soc.svg?800|}}
 +
 +The design has one JESD receive chain with 4 lanes at rate of 10Gbps. The JESD receive chain consists of a physical and link layer represented by AD9083_JESD204 module, and transport layer represented by a AXI_AD9083 module. The links operate in Subclass 0 since it is not using the SYSREF signal.
  
 ==== Building the HDL project ==== ==== Building the HDL project ====
resources/eval/user-guides/ad9083/ad9083_evb_reference_hdl.txt · Last modified: 17 Nov 2022 15:24 by Liviu-Mihai Iacob