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| resources:eval:user-guides:ad9081_fmca_ebz:ad9081_fmca_ebz_hdl [28 Jul 2021 13:06] – [DAC - crossbar config] Laszlo Nagy | resources:eval:user-guides:ad9081_fmca_ebz:ad9081_fmca_ebz_hdl [25 Nov 2021 07:02] – [AD9081-FMCA-EBZ/AD9082-FMCA-EBZ (Single MxFE) HDL Reference Design] Laszlo Nagy | ||
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| - | ====== AD9081-FMCA-EBZ (Single MxFE) HDL Reference Design ====== | + | ====== AD9081-FMCA-EBZ / AD9082-FMCA-EBZ (Single MxFE) HDL Reference Design ====== |
| ===== Functional Overview ===== | ===== Functional Overview ===== | ||
| - | The AD9081-FMCA-EBZ reference design is a processor based (e.g. Microblaze) embedded system. The design consists from a receive and a transmit chain. | + | The AD9081-FMCA-EBZ / AD9082-FMCA-EBZ reference design is a processor based (e.g. Microblaze) embedded system. The design consists from a receive and a transmit chain. |
| The receive chain transports the captured samples from ADC to the system memory (DDR). Before transferring the data to DDR the samples are stored in a buffer implemented on block rams from the FPGA fabric (util_adc_fifo). | The receive chain transports the captured samples from ADC to the system memory (DDR). Before transferring the data to DDR the samples are stored in a buffer implemented on block rams from the FPGA fabric (util_adc_fifo). | ||
resources/eval/user-guides/ad9081_fmca_ebz/ad9081_fmca_ebz_hdl.txt · Last modified: 15 Apr 2024 12:26 by iulia Moldovan