Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
Next revisionBoth sides next revision
resources:eval:user-guides:ad9081_fmca_ebz:ad9081_fmca_ebz_hdl [07 Apr 2021 07:07] – [Example block design for Single Link; M=2; L=8; JESD204C] Laszlo Nagyresources:eval:user-guides:ad9081_fmca_ebz:ad9081_fmca_ebz_hdl [14 Jun 2021 07:37] – [Example block design for Single Link; M=2; L=8; JESD204C] Laszlo Nagy
Line 49: Line 49:
 # Parameter description: # Parameter description:
 #    JESD_MODE : used link layer encoder mode  #    JESD_MODE : used link layer encoder mode 
-#      64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer +#      64B66B - 64b66b link layer defined in JESD 204C 
-#      8B10B  - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer+#      8B10B  - 8b10b link layer defined in JESD 204B
 #     #    
-#    RX_RATE :  line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode  +#    RX_RATE :  line rate of the Rx link ( MxFE to FPGA )  
-#    TX_RATE :  line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode  +#    TX_RATE :  line rate of the Tx link ( FPGA to MxFE )
-#    REF_CLK_RATE : frequency of reference clock in MHz used in 64B66B mode+
 #    [RX/TX]_JESD_M : number of converters per link #    [RX/TX]_JESD_M : number of converters per link
 #    [RX/TX]_JESD_L : number of lanes per link #    [RX/TX]_JESD_L : number of lanes per link
Line 78: Line 77:
  
   * NP = 8, 12, 16   * NP = 8, 12, 16
-  * F = 1, 2, 3, 4, 6+  * F = 1, 2, 3, 4, 6, 8
   * https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx#restrictions   * https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx#restrictions
   * https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx#restrictions   * https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx#restrictions
Line 145: Line 144:
  
 ==== Example block design for Single Link; M=2; L=8; JESD204C ====  ==== Example block design for Single Link; M=2; L=8; JESD204C ==== 
 +
 +Observation: In 2019_R2 release the Xilinx JESD Physical layer IP Core is used, however in newer versions it is replaced with ADI's util_adxcvr IP core. 
  
 {{ :resources:eval:user-guides:ad9081_fmca_ebz:ad9081_204c_m2l8.svg |}} {{ :resources:eval:user-guides:ad9081_fmca_ebz:ad9081_204c_m2l8.svg |}}
Line 178: Line 179:
   * REF_CLK – 500 MHz (Lane Rate/33)   * REF_CLK – 500 MHz (Lane Rate/33)
   * JESD204C Lane Rate – 16.5Gbps   * JESD204C Lane Rate – 16.5Gbps
-  * QPLL1 - selected in Xilinx PHY +  * QPLL1
  
 The Tx link is operating with the following parameters: The Tx link is operating with the following parameters:
Line 187: Line 188:
   * REF_CLK – 500 MHz (Lane Rate/33)   * REF_CLK – 500 MHz (Lane Rate/33)
   * JESD204C Lane Rate – 16.5Gbps   * JESD204C Lane Rate – 16.5Gbps
-  * QPLL1 - selected in Xilinx PHY +  * QPLL1 
    
 ===== Clock sources ===== ===== Clock sources =====
resources/eval/user-guides/ad9081_fmca_ebz/ad9081_fmca_ebz_hdl.txt · Last modified: 15 Apr 2024 12:26 by iulia Moldovan

Page Tools