This version (09 Jan 2021 00:35) was approved by Robin Getz.The Previously approved version (08 Dec 2020 13:52) is available.Diff

AD7768-EVB Bare Metal Quick Start Guide


The AD7768 is an 8-channel simultaneous sampling sigma-delta (Σ-Δ) analog-to-digital converter (ADC), respectively, with a Σ-Δ modulator and digital filter per channel, enabling synchronized sampling of ac and dc signals.

The AD7768 achieves 108 dB dynamic range at a maximum input bandwidth of 110.8 kHz, combined with typical performance of ±2 ppm integral nonlinearity (INL), ±50 μV offset error, and ±30 ppm gain error.

The AD7768 user can trade off input bandwidth, output data rate, and power dissipation, and select one of three power modes to optimize for noise targets and power consumption. The flexibility of the AD7768 allows it to become a reusable platform for low power dc and high performance ac measurement module.

The AD7768 has three modes: fast mode (256 kSPS maximum, 110.8 kHz input bandwidth, 51.5 mW per channel), median mode (128 kSPS maximum, 55.4 kHz input bandwidth, 27.5 mW per channel) and low power mode (32 kSPS maximum, 13.8 kHz input bandwidth, 9.375 mW per channel).

The AD7768 offers extensive digital filtering capabilities, such as a wideband, low ±0.005 dB pass-band ripple, antialiasing low-pass filter with sharp roll-off, and 105 dB attenuation at the Nyquist frequency.

Frequency domain measurements can use the wideband linear phase filter. This filter has a flat pass band (±0.005 dB ripple) from dc to 102.4 kHz at 256 kSPS, from dc to 51.2 kHz at 128 kSPS, or from dc to 12.8 kHz at 32 kSPS.

The AD7768 also offers sinc response via a sinc5 filter, a low latency path for low bandwidth, and low noise measurements. The wideband and sinc5 filters can be selected and run on a per channel basis.

Within these filter options, the user can improve the dynamic range by selecting from decimation rates of ×32, ×64, ×128, ×256, ×512, and ×1024. The ability to vary the decimation filtering optimizes noise performance to the required input bandwidth.

Embedded analog functionality on each ADC channel makes design easier, such as a precharge buffer on each analog input that reduces analog input current and a precharge reference buffer per channel reduces input current and glitches on the reference input terminals.

The device operates with a 5 V AVDD1A and AVDD1B supply, a 2.25 V to 5.0 V AVDD2A and AVDD2B supply, and a 2.5 V to 3.3 V or 1.8 V IOVDD supply (see the 1.8 V IOVDD Operation section for specific requirements for operating at 1.8 V IOVDD).

The device requires an external reference; the absolute input reference voltage range is 1 V to AVDD1 − AVSS.

The specified operating temperature range is −40°C to +105°C. The device is housed in a 10 mm × 10 mm 64-lead LQFP package with a 12 mm × 12 mm printed circuit board (PCB) footprint.

Supported devices

Evaluation boards

Supported FPGA carrier

HDL Design Description

In the ADI Reference Designs HDL User Guide can be found an in-depth presentation and instructions about the HDL design in general.

In order to build the HDL design the user has to go through the following steps:

  1. Confirm that you have the right tools (see Release notes)
  2. Clone the HDL GitHub repository (see

The HDL architecture comprises a serial data path that enables all the ADC channels and a parallel data path, so that the user can enable only the desired channels.

HDL block diagram

HDL Downloads

No-OS Downloads

resources/eval/user-guides/ad7768-ebz/software/baremetal.txt · Last modified: 09 Jan 2021 00:32 by Robin Getz