This version (27 Mar 2023 12:34) was approved by Alin-Tudor Sferle.The Previously approved version (02 Jan 2023 21:35) is available.Diff

AD7606X HDL Reference Design


The EVAL-AD7606B-FMCZ and EVAL-AD7606C-18 evaluation boards are designed to help users to easily evaluate the features of AD7606B, AD7606C-16 and AD7606C-18 analog-to-digital converters (ADCs).

Used devices

Evaluation board

Supported FPGA carrier

Reference HDL Design

The design is built upon ADI's generic HDL reference design framework. In the ADI Reference Designs HDL User Guide can be found an in-depth presentation and instructions about the HDL design framework in general.

Block diagram

  • AD7606X_FMC using the PARALLEL interface

Required software

  • We're upgrading the Xilinx tools on every release. The supported version number can be found in our git repository .
  • An UART terminal (Tera Term/Hyperterminal), baud rate set to 115200.


Parameter name Default value Description
DEV_CONFIG 0 Device that will be used: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18
SIMPLE_STATUS_CRC 0 ADC Read Mode options: 0 - Simple, 1 - STATUS, 2 - CRC, 3 - STATUS_CRC
EXT_CLK 0 External clock option for the ADC clock: No(0), Yes(1)

Using the HDL reference design

In the ADI Reference Designs HDL User Guide can be found an in-depth presentation and instructions about the HDL design in general.

In the axi_ad7606x's wiki page, can be found a detailed description of the core.

The data path of the HDL design is simple as follows:

  • the parallel interface is controlled by the axi_ad7606x IP core
  • the serial interface is controlled by the SPI Engine Framework
  • data is written into memory by a DMA (axi_dmac core)
  • all the control pins of the device are driven by GPIO's

In order to build the HDL design the user has to go through the following steps:

  1. Confirm that you have the right tools (see Release notes)
  2. Clone the HDL GitHub repository (see
  3. Choose the required interface (see caption Switching between interface types)

Switching between device types, operation modes and clocking option

Before the board power-up, the user has to choose the device type, operation mode and clocking option. Depending on the operation mode, some hardware modifications need to be done on the board and/or Tcl script:

In case of the AD7606C-16 device:

$ make DEV_CONFIG=1

In case of the STATUS operation mode:


PL Interrupts

Instance HDL interrupt Linux PsU interrupt
0 89
1 90
2 91
3 92
4 93
5 94
6 95
7 96
8 104
9 105
10 106
11 107
12 108
axi_ad7606x_dma 13 109
14 110
15 111

GPIO signals

Ps7 EMIO offset = 54

adc_serpar 93 39
adc_refsel 92 38
adc_reset 91 37
adc_stby 90 36
adc_range 89-87 35
adc_os 86 34-32

Register Map

The register map of the core contains instances of three generic register maps: Base, ADC common and ADC channel. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.

Base (common to all cores)

Click to expand regmap

ADC Common (axi_ad*)

Click to expand regmap

ADC Channel (axi_ad*)

Click to expand regmap

HDL Downloads


Questions? Feel free to ask your questions in EngineerZone support forums.

resources/eval/user-guides/ad7606x-fmc/hdl.txt · Last modified: 27 Mar 2023 12:34 by Alin-Tudor Sferle