The design is built upon ADI's generic HDL reference design framework. In the ADI Reference Designs HDL User Guide can be found an in-depth presentation and instructions about the HDL design framework in general.
|Parameter name||Default value||Description|
|DEV_CONFIG||0||Device that will be used: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18|
|SIMPLE_STATUS_CRC||0||ADC Read Mode options: 0 - Simple, 1 - STATUS, 2 - CRC, 3 - STATUS_CRC|
|EXT_CLK||0||External clock option for the ADC clock: No(0), Yes(1)|
In the ADI Reference Designs HDL User Guide can be found an in-depth presentation and instructions about the HDL design in general.
In the axi_ad7606x's wiki page, can be found a detailed description of the core.
The data path of the HDL design is simple as follows:
In order to build the HDL design the user has to go through the following steps:
Before the board power-up, the user has to choose the device type, operation mode and clocking option. Depending on the operation mode, some hardware modifications need to be done on the board and/or Tcl script:
In case of the AD7606C-16 device:
$ make DEV_CONFIG=1
In case of the STATUS operation mode:
$ make SIMPLE_STATUS_CRC=1
|Instance||HDL interrupt||Linux PsU interrupt|
Ps7 EMIO offset = 54
|GPIO Signal||GPIO||HDL GPIO EMIOn|
The register map of the core contains instances of three generic register maps: Base, ADC common and ADC channel. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.