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resources:eval:user-guides:ad738x [30 Sep 2019 12:35] – [HDL Design Description] Stanca-Florina Pop | resources:eval:user-guides:ad738x [18 Oct 2019 11:54] – [Overview] jonathan colao | ||
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* [[adi> | * [[adi> | ||
* [[adi> | * [[adi> | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
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===== Overview ===== | ===== Overview ===== | ||
- | The [[adi> | + | The [[adi> |
bit pin compatible family of dual simultaneous sampling, high | bit pin compatible family of dual simultaneous sampling, high | ||
speed, low power, successive approximation analog-to-digital | speed, low power, successive approximation analog-to-digital | ||
converters (ADC) that operate from a 3.3 V power supply and | converters (ADC) that operate from a 3.3 V power supply and | ||
- | features throughput rates up to 4 MSPS for the [[adi> | + | features throughput rates up to 4 MSPS. The analog input type is |
- | [[adi> | + | differential |
- | differential, accept a wide common mode input voltage and are | + | [[adi> |
- | sampled and converted on the falling edge of CS. | + | sampled and converted on the falling edge of CS. The [[adi> |
The [[adi> | The [[adi> | ||
blocks to improve dynamic range and reduce noise at lower | blocks to improve dynamic range and reduce noise at lower |