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This version (22 Jul 2019 10:07) was approved by AndreiD1994.The Previously approved version (17 May 2018 22:50) is available.Diff

AD6676-EBZ Bare Metal Quick Start Guide

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AD6676 Driver Description

Functions Declarations

Function Description
int32_t ad6676_spi_read(struct ad6676_dev *dev, uint16_t reg_addr, uint8_t *reg_data);
SPI read from device.
int32_t ad6676_spi_write(struct ad6676_dev *dev, uint16_t reg_addr, uint8_t reg_data);
SPI write to device.
static int32_t ad6676_set_splitreg(struct ad6676_dev *dev, uint32_t reg, uint32_t val);
SPI write a 16 bit register as two consecutive registers, LSB first.
static inline int32_t ad6676_get_splitreg(struct ad6676_dev *dev, uint32_t reg, uint32_t *val);
SPI read from a 16 bit register as two consecutive registers, LSB first.
static int32_t ad6676_set_fadc(struct ad6676_dev *dev, uint32_t val);
Set ADC clock frequency.
static inline uint32_t ad6676_get_fadc(struct ad6676_dev *dev);
Get the ADC clock frequency.
int32_t ad6676_set_fif(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
Set the target IF frequency.
uint64_t ad6676_get_fif(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
Get the target IF frequency.
static int32_t ad6676_set_bw(struct ad6676_dev *dev, uint32_t val);
Set the target BW frequency.
static inline uint32_t ad6676_get_bw(struct ad6676_dev *dev);
Get the target BW frequency.
static int32_t ad6676_set_decimation(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
Set decimation factor in the decimation mode register.
static int32_t ad6676_set_clk_synth(struct ad6676_dev *dev, uint32_t refin_Hz, uint32_t freq);
Set the clock synthesizer to generate a specific frequency using a given refrence clock and do VCO and CP calibration.
static int32_t ad6676_set_extclk_cntl(struct ad6676_dev *dev, uint32_t freq);
Enable external clock for the ADC.
static int32_t ad6676_jesd_setup(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
Setup JESD204 link parameters.
int32_t ad6676_shuffle_setup(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
Setup shuffling rate and threshold for the adaptive shuffler.
static int32_t ad6676_calibrate(struct ad6676_dev *dev, uint32_t cal);
Do internal calibration of JESD, ADC or flash.
static int32_t ad6676_reset(struct ad6676_dev *dev, uint8_t spi3wire);
Software reset all SPI registers to default value.
static int32_t ad6676_outputmode_set(struct ad6676_dev *dev, uint32_t mode);
Set output mode as twos complement or straight binary.
int32_t ad6676_set_attenuation(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
Set attenuation in decibels or disable attenuator.
int32_t ad6676_setup(struct ad6676_dev **device, struct ad6676_init_param init_param);
Initialize the device.
int32_t ad6676_update(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
Reconfigure device for other target frequency and bandwidth and recalibrate.
int32_t ad6676_test(struct ad6676_dev *dev, uint32_t test_mode);
Perform an interface test.

Make

Build no-OS with GNU make

This guide provides some quick instructions on how to build and run the no-OS on almost all of the supported platforms.

Be sure you are using the latest release version and you have the corresponding branches for both HDL and no-OS(Release notes).

Building the HDL

ADI does not distribute the bit/elf files of these projects. They must be built from the sources. The HDL User Guide provides detailed information and steps to build the HDL project on your desired carrier. The build flow is developed around GNU make. You may use a Windows or Linux OS, but do NOT seek OS- specific support. The prerequisite to the building process is that you are able to run 'quartus', 'vivado' and 'make' all from a shell (Cygwin or Linux).

Building the HDL is as simple as running make on your desired project and carrier.

hdl/projects/daq3/kcu105> make
hdl/projects/daq3/zc706> make
For Intel nios2 based processor projects you have to turn off the MMU (Memory Management Unit used for Linux OS) when building the HDL.
hdl/projects/daq3/a10gx> make MMU=0

We strongly recommend having a clone of no-Os and HDL in the same folder:

  ~/github/hdl/
  ~/github/no-OS/

In every project folder, you can find a separate subfolder for each supported carrier. In each carrier folder, there is a Makefile which points to the bit files and HDL deliverables (system_top.hdf/project_name.sof) and other makefiles (*.mk) containing the software dependencies.

Building the software

Change your current directory to your targeted project and run make:

  [~] cd fmcdaq2/zc706 
  [~] make

See Troubleshooting section for guideline how to solve make related issues.

Running the software

Make sure that the FPGA is powered on and connected to the PC and then run the command:

  [~] make run

The make run will downloads the bitstream on the FPGA and after that program the board with the elf file.

The software is started before the memory debugger disconnects.

Evaluating the result

After the software has been run on the FPGA, run the command:

  [~] make capture

By default, the software captures (in case of ADC based projects) the data received from the device in the RAM.

  rx_xfer.start_address = *_MEM_BASEADDR + OFFSET;
  rx_xfer.no_of_samples = value;
  dmac_start_transaction(ad_core_dma);

These values differ depending on the architecture and device.

The Makefiles have these parameters initialized with default values:

The number of samples is specified in the project's common Makefile. (ex: fmcadc4)

The script will write a capture_chx.csv file for every channel.
In the case of an RF device which has I and Q data for each channel, the number of capture_chx.csv files will double.

For example, for fmcomms2(AD9361: 2RF channels):

fmcomms2
channel1 data I capture_ch1.csv
data Q capture_ch2.csv
channel2 data I capture_ch3.csv
data Q capture_ch4.csv

Clean the workspace

  [~] make clean

Troubleshooting

  make: *** No rule to make target `../../../hdl/projects/daq2/vc707/daq2_vc707.sdk/system_top.hdf', needed by `hw/system_top.bit'.  Stop.

The HDL deliverables cannot be found. Maybe the targeted HDL project is not built, or the defined path is not valid. Make sure, that you build the HDL before running the no-OS or specify the location of the HDL deliverables explicitly.

  • Specify HDL location:

For Xilinx

  [~] make M_HDF_FILE=/<path_to_hdf>/system_top.hdf

For Intel

  [~] make M_SOPCINFO_FILE=/<path_to_sopcinfo>/system_bd.sopcinfo

Understanding/Modifying things

The best place to start in the no-OS main function in “project/project_name.c”. It shows how individual components of a data path chain are initialized and programmed for the application. After you have the default setup working, feel free to add your own customization routines and/or signal processing functions to either HDL or no-OS.

Navigation - Build no-OS with GNU make

13 Mar 2018 16:39 · andrei_g

GUI

  • Open Xilinx Software Development Kit (XSDK) and provide the workspace location.
  • Create a new Application Project: go to File → New → Application Project

Creating a new application project

  • Create a new Hardware Platform: click New from the Target Hardware section

Creating a new hardware platform

Import hardware description file

  • Give a name to the project and to the board support package and click Next

Application project settings

  • Select the Empty Application templeta and click Finish

Choose application template

  • The new Empty Application project should look like:

Empty application project

Some applications (e.g. FMCOMMSx), when a Microblaze processor is used, requires an increased HEAP size for dynamic memory allocation. Make sure the HEAP size is at least 0x100000.
  • Copy the source code files into the src directory
  • If there are multiple folders present in in the src one, include all the paths of the folders: go to the settings of the project and in the C/C++ Build → Settings → Tool Settings → gcc compiler → Directories section and add the paths of all the folders.
  • The SDK should automatically build the projects and the Console window will display the result of the build. If the build is not done automatically select the Project → Build Automatically menu option.
  • At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. You can program the FPGA by clicking on Xilinx Tools → Program FPGA
  • After the FPGA was programmed, we need to create a new Run configuration, by selecting RunRun Configurations…, in the Run Configuration windows select the Xilinx C/C++ application (GDB) and click at the New Configuration button at the upper left corner.

Create new run configuration

  • If your target carrier has a Zync SoC, make sure, that you specify the Initialization file, and select the Run ps7_init and Run ps7_post_config options.

Define Zynq initialization file

  • At the Application tab define your current project name and application executable. (.elf)

Define Zynq initialization file

  • The output of the example program can be viewed in the SDK console by enabling the Connect STDIO Console option and setting the baud rate of the UART port to 115200.

Define Zynq initialization file

  • As an alternative a UART terminal can be used to capture the output of the example program. The number of used UART port depends on the computer's configuration. The following settings must be used in the UART terminal:
  • Baud Rate: 115200bps
  • Data: 8 bit
  • Parity: None
  • Stop bits: 1 bit
  • Flow Control: none
  • When the run configuration is done, the software can be started by clicking the Run button.
  • Your new bare metal application should run
27 Feb 2015 14:57 · CsomI
resources/eval/user-guides/ad6676-ebz/software/baremetal.txt · Last modified: 22 Jul 2019 10:06 by AndreiD1994