int32_t ad6676_spi_read(struct ad6676_dev *dev, uint16_t reg_addr, uint8_t *reg_data);
|SPI read from device.|
int32_t ad6676_spi_write(struct ad6676_dev *dev, uint16_t reg_addr, uint8_t reg_data);
|SPI write to device.|
static int32_t ad6676_set_splitreg(struct ad6676_dev *dev, uint32_t reg, uint32_t val);
|SPI write a 16 bit register as two consecutive registers, LSB first.|
static inline int32_t ad6676_get_splitreg(struct ad6676_dev *dev, uint32_t reg, uint32_t *val);
|SPI read from a 16 bit register as two consecutive registers, LSB first.|
static int32_t ad6676_set_fadc(struct ad6676_dev *dev, uint32_t val);
|Set ADC clock frequency.|
static inline uint32_t ad6676_get_fadc(struct ad6676_dev *dev);
|Get the ADC clock frequency.|
int32_t ad6676_set_fif(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
|Set the target IF frequency.|
uint64_t ad6676_get_fif(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
|Get the target IF frequency.|
static int32_t ad6676_set_bw(struct ad6676_dev *dev, uint32_t val);
|Set the target BW frequency.|
static inline uint32_t ad6676_get_bw(struct ad6676_dev *dev);
|Get the target BW frequency.|
static int32_t ad6676_set_decimation(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
|Set decimation factor in the decimation mode register.|
static int32_t ad6676_set_clk_synth(struct ad6676_dev *dev, uint32_t refin_Hz, uint32_t freq);
|Set the clock synthesizer to generate a specific frequency using a given refrence clock and do VCO and CP calibration.|
static int32_t ad6676_set_extclk_cntl(struct ad6676_dev *dev, uint32_t freq);
|Enable external clock for the ADC.|
static int32_t ad6676_jesd_setup(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
|Setup JESD204 link parameters.|
int32_t ad6676_shuffle_setup(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
|Setup shuffling rate and threshold for the adaptive shuffler.|
static int32_t ad6676_calibrate(struct ad6676_dev *dev, uint32_t cal);
|Do internal calibration of JESD, ADC or flash.|
static int32_t ad6676_reset(struct ad6676_dev *dev, uint8_t spi3wire);
|Software reset all SPI registers to default value.|
static int32_t ad6676_outputmode_set(struct ad6676_dev *dev, uint32_t mode);
|Set output mode as twos complement or straight binary.|
int32_t ad6676_set_attenuation(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
|Set attenuation in decibels or disable attenuator.|
int32_t ad6676_setup(struct ad6676_dev **device, struct ad6676_init_param init_param);
|Initialize the device.|
int32_t ad6676_update(struct ad6676_dev *dev, struct ad6676_init_param *init_param);
|Reconfigure device for other target frequency and bandwidth and recalibrate.|
int32_t ad6676_test(struct ad6676_dev *dev, uint32_t test_mode);
|Perform an interface test.|
This guide provides some quick instructions on how to build and run the no-OS on almost all of the supported platforms.
Be sure you are using the latest release version and you have the corresponding branches for both HDL and no-OS(Release notes).
ADI does not distribute the bit/elf files of these projects. They must be built from the sources. The HDL User Guide provides detailed information and steps to build the HDL project on your desired carrier. The build flow is developed around GNU make. You may use a Windows or Linux OS, but do NOT seek OS- specific support. The prerequisite to the building process is that you are able to run 'quartus', 'vivado' and 'make' all from a shell (Cygwin or Linux).
Building the HDL is as simple as running make on your desired project and carrier.
hdl/projects/daq3/kcu105> make hdl/projects/daq3/zc706> make
hdl/projects/daq3/a10gx> make MMU=0
We strongly recommend having a clone of no-Os and HDL in the same folder:
In every project folder, you can find a separate subfolder for each supported carrier. In each carrier folder, there is a Makefile which points to the bit files and HDL deliverables (system_top.hdf/project_name.sof) and other makefiles (*.mk) containing the software dependencies.
Change your current directory to your targeted project and run make:
[~] cd fmcdaq2/zc706 [~] make
See Troubleshooting section for guideline how to solve make related issues.
Make sure that the FPGA is powered on and connected to the PC and then run the command:
[~] make run
The make run will downloads the bitstream on the FPGA and after that program the board with the elf file.
The software is started before the memory debugger disconnects.
After the software has been run on the FPGA, run the command:
[~] make capture
By default, the software captures (in case of ADC based projects) the data received from the device in the RAM.
rx_xfer.start_address = *_MEM_BASEADDR + OFFSET; rx_xfer.no_of_samples = value; dmac_start_transaction(ad_core_dma);
These values differ depending on the architecture and device.
The Makefiles have these parameters initialized with default values:
The number of samples is specified in the project's common Makefile. (ex: fmcadc4)
For example, for fmcomms2(AD9361: 2RF channels):
[~] make clean
make: *** No rule to make target `../../../hdl/projects/daq2/vc707/daq2_vc707.sdk/system_top.hdf', needed by `hw/system_top.bit'. Stop.
The HDL deliverables cannot be found. Maybe the targeted HDL project is not built, or the defined path is not valid. Make sure, that you build the HDL before running the no-OS or specify the location of the HDL deliverables explicitly.
[~] make M_HDF_FILE=/<path_to_hdf>/system_top.hdf
[~] make M_SOPCINFO_FILE=/<path_to_sopcinfo>/system_bd.sopcinfo
The best place to start in the no-OS main function in “project/project_name.c”. It shows how individual components of a data path chain are initialized and programmed for the application. After you have the default setup working, feel free to add your own customization routines and/or signal processing functions to either HDL or no-OS.
//#define XILINX #define ALTERA