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resources:eval:user-guides:ad469x [10 Dec 2020 11:26] Cristian Pop [Functions Declarations] |
resources:eval:user-guides:ad469x [14 Jan 2021 05:11] Robin Getz user interwiki links |
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| {{:resources:fpga:docs:ad469x_hdl1.svg|spi engine block diagram}} | {{:resources:fpga:docs:ad469x_hdl1.svg|spi engine block diagram}} | ||
| - | The reference design uses the standard [[https://wiki.analog.com/resources/fpga/peripherals/spi_engine|SPI Engine Framework]] to interface the AD4696 ADC in single SDO Mode. The SPI offload module, which can be used to capture continuous data stream at maximum data rate, is triggered by the BUSY signal of the device. | + | The reference design uses the standard [[/resources/fpga/peripherals/spi_engine|SPI Engine Framework]] to interface the AD4696 ADC in single SDO Mode. The SPI offload module, which can be used to capture continuous data stream at maximum data rate, is triggered by the BUSY signal of the device. |
| In order to build the HDL design the user has to go through the following steps: | In order to build the HDL design the user has to go through the following steps: | ||
resources/eval/user-guides/ad469x.txt · Last modified: 14 Jan 2021 05:11 by Robin Getz