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resources:eval:user-guides:ad469x [10 Dec 2020 11:23] – [No-OS Driver Description] Cristian Popresources:eval:user-guides:ad469x [14 Jan 2021 05:11] (current) – user interwiki links Robin Getz
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 {{:resources:fpga:docs:ad469x_hdl1.svg|spi engine block diagram}} {{:resources:fpga:docs:ad469x_hdl1.svg|spi engine block diagram}}
  
-The reference design uses the standard [[https://wiki.analog.com/resources/fpga/peripherals/spi_engine|SPI Engine Framework]] to interface the AD4696 ADC in single SDO Mode. The SPI offload module, which can be used to capture continuous data stream at maximum data rate, is triggered by the BUSY signal of the device. +The reference design uses the standard [[/resources/fpga/peripherals/spi_engine|SPI Engine Framework]] to interface the AD4696 ADC in single SDO Mode. The SPI offload module, which can be used to capture continuous data stream at maximum data rate, is triggered by the BUSY signal of the device. 
  
 In order to build the HDL design the user has to go through the following steps: In order to build the HDL design the user has to go through the following steps:
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      struct ad469x_init_param *init_param);</code>| Initialize the device |      struct ad469x_init_param *init_param);</code>| Initialize the device |
 |<code c>int32_t ad469x_remove(struct ad469x_dev *dev);</code>| Remove the device and release resources | |<code c>int32_t ad469x_remove(struct ad469x_dev *dev);</code>| Remove the device and release resources |
 +
 +==== Types Declarations ====
 +
 +|<code c>
 +/**
 + * @enum ad469x_channel_sequencing
 + * @brief Channel sequencing modes
 + */
 +enum ad469x_channel_sequencing {
 + /** Single cycle read */
 + AD469x_single_cycle,
 + /** Two cycle read */
 + AD469x_two_cycle,
 + /** Sequence trough channels, standard mode */
 + AD469x_standard_seq,
 + /** Sequence trough channels, advanced mode */
 + AD469x_advanced_seq,
 +};
 +
 +/**
 +  * @enum ad469x_busy_gp_sel
 +  * @brief Busy state, possible general purpose pin selections
 +  */
 +enum ad469x_busy_gp_sel {
 + /** Busy on gp0 */
 + AD469x_busy_gp0 = 0,
 + /** Busy on gp3 */
 + AD469x_busy_gp3 = 1,
 +};
 +
 +/**
 +  * @enum ad469x_reg_access
 +  * @brief Register access modes
 +  */
 +enum ad469x_reg_access {
 + AD469x_BYTE_ACCESS,
 + AD469x_WORD_ACCESS,
 +};
 +
 +/**
 +  * @enum ad469x_supported_dev_ids
 +  * @brief Supported devices
 +  */
 +enum ad469x_supported_dev_ids {
 + ID_AD4695,
 + ID_AD4696,
 + ID_AD4697,
 +};
 +
 +/**
 +  * @enum ad469x_osr_ratios
 +  * @brief Supported oversampling ratios
 +  */
 +enum ad469x_osr_ratios {
 + AD469x_OSR_1,
 + AD469x_OSR_4,
 + AD469x_OSR_16,
 + AD469x_OSR_64
 +};
 +
 +/**
 + * @struct ad469x_init_param
 + * @brief  Structure containing the init parameters needed by the ad469x device
 + */
 +struct ad469x_init_param {
 + /* SPI */
 + spi_init_param *spi_init;
 + /* SPI module offload init */
 + struct spi_engine_offload_init_param *offload_init_param;
 + /* PWM generator init structure */
 + struct pwm_init_param *trigger_pwm_init;
 + /** RESET GPIO initialization structure. */
 + struct gpio_init_param *gpio_resetn;
 + /* Clock gen for hdl design init structure */
 + struct axi_clkgen_init *clkgen_init;
 + /* Clock generator rate */
 + uint32_t axi_clkgen_rate;
 + /* Register access speed */
 + uint32_t reg_access_speed;
 + /* Register data width */
 + uint8_t reg_data_width;
 + /* Capture data width */
 + uint8_t capture_data_width;
 + /* Device Settings */
 + enum ad469x_supported_dev_ids dev_id;
 + /** Invalidate the Data cache for the given address range */
 + void (*dcache_invalidate_range)(uint32_t address, uint32_t bytes_count);
 +};
 +
 +/**
 + * @struct ad469x_dev
 + * @brief  Structure representing an ad469x device
 + */
 +struct ad469x_dev {
 + /* SPI descriptor */
 + spi_desc *spi_desc;
 + /* Clock gen for hdl design structure */
 + struct axi_clkgen *clkgen;
 + /* Trigger conversion PWM generator descriptor */
 + struct pwm_desc *trigger_pwm_desc;
 + /* SPI module offload init */
 + struct spi_engine_offload_init_param *offload_init_param;
 + /* Register access speed */
 + uint32_t reg_access_speed;
 + /* Register data width */
 + uint8_t reg_data_width;
 + /* Capture data width */
 + uint8_t capture_data_width;
 + /* Device Settings */
 + enum ad469x_supported_dev_ids dev_id;
 + /** RESET GPIO handler. */
 + struct gpio_desc *gpio_resetn;
 + /** Invalidate the Data cache for the given address range */
 + void (*dcache_invalidate_range)(uint32_t address, uint32_t bytes_count);
 + /** Current channel sequence */
 + enum ad469x_channel_sequencing ch_sequence;
 + /** OSR resolution corresponding to each channel, when advanced
 + * sequencer is selected. */
 + enum ad469x_osr_ratios adv_seq_osr_resol[AD469x_CHANNEL_NO];
 + /** Channel slots for advanced sequencer */
 + uint8_t ch_slots[AD469x_SLOTS_NO];
 + /** Temperature enabled for standard and advanced sequencer if set. */
 + bool temp_enabled;
 + /** Number of active channel slots, for advanced sequencer */
 + uint8_t num_slots;
 +};
 +</code>|
 ===== HDL Downloads ===== ===== HDL Downloads =====
 <WRAP round download 50%> <WRAP round download 50%>
resources/eval/user-guides/ad469x.txt · Last modified: 14 Jan 2021 05:11 by Robin Getz

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