This version (15 Feb 2022 10:43) was approved by Antoniu Miclaus.The Previously approved version (14 Feb 2022 14:49) is available.
Table of Contents
AD-FMCXMWBR1-EBZ HDL Reference Design
Supported Devices
Supported Carriers
HDL Design Description
The design is built upon ADI's generic HDL reference design framework. More information about the framework can be found in the ADI Reference Designs HDL User Guide wiki page.
The reference design uses SPI and I2C to interface with the AD-FMCXMWBR1 FMC bridge.
For more details regarding the digital interface, check the main ADRV9009ZU11EG HDL Reference Design wiki page.
In order to build the HDL design the user has to go through the following steps:
- Confirm that you have the right tools (see Release notes)
- Clone the HDL GitHub repository (see https://wiki.analog.com/resources/fpga/docs/git)
- Build the project (see https://wiki.analog.com/resources/fpga/docs/build)
Control and SPI
The device control and monitor signals are interfaced to a GPIO module. The SPI/I2C signals are controlled by a separate AXI based SPI/I2C core.
AD-FMCXMWBR1-EBZ Specific Boot Files
Help & Support
- The carriers (abbrevations can be found here) are commonly available FPGA evaluation boards.
- The HDL user guide contains all the documentation, build instructions and register map tables.
- The following quick links allows you to browse the github repository for a list of current branches, library components, and projects.
resources/eval/user-guides/ad-fmcxmwbr1-ebz/reference_hdl.txt · Last modified: 15 Feb 2022 10:43 by Antoniu Miclaus