The most recent version of this page is a draft.
This version is outdated by a newer approved version.This version (10 Jul 2015 23:12) is a draft.
Approvals: 0/1The Previously approved version (02 Dec 2014 20:48) is available.
This version is outdated by a newer approved version.This version (10 Jul 2015 23:12) is a draft.Approvals: 0/1The Previously approved version (02 Dec 2014 20:48) is available.
This is an old revision of the document!
Table of Contents
AD-FMCOMMS5-EBZ Hardware
Downloads
- Rev B Allegro Board File (This file is compressed). Get the Allegro FREE Physical Viewer (You need 16.5 or higher).
ERRATA:
The FMCOMMS5, REV B has a bug in it, that doesn't allow the ADF5355 to function properly. (Pin 5, AVDD is a floating node). It's a simple fix - short pin 5 (AVDD) with pin 4 (CE) to make a connection to VDD_EXT_LO_3P3.
I/O Voltage
The AD-FMComms5 (AD9361) assumes a VDD_INTERFACE voltage between 1.71V and 2.625V (1.8 to 2.5 +/- 5%), so on your FPGA carrier board, you should ensure that VADJ is between these levels. Setting things to 3.3V will damage the part.
resources/eval/user-guides/ad-fmcomms5-ebz/hardware.1436562746.txt.gz · Last modified: 10 Jul 2015 23:12 by Robin Getz